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158 条记录 (耗时 0.038 秒)

    Semiconductor devices
    71.
    发明授权
    Semiconductor devices 失效
    半导体器件

    公开(公告)号：US07538409B2

    公开(公告)日：2009-05-26

    申请号：US11422690

    申请日：2006-06-07

    申请人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

    发明人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

    IPC分类号： H01L29/00

    CPC分类号： H01L29/7436 ,  H01L27/0262 ,  H01L29/7378

    摘要： A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises a reach-through structure connecting the first and second sub-collectors and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. The device further comprises N+ diffusion regions in contact with the N-well, a P+ diffusion region in contact with the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.

    摘要翻译： 一种器件包括形成在衬底的上部中的第一子集电极和形成在第一外延层的上部中的第一外延层和第二子集电极的下部，以及第二外延层的下部 。 该装置还包括连接第一和第二子集电器的连通结构和形成在第二外延层的一部分中并与第二子集电器和达到通孔结构接触的N阱。 该装置还包括与N阱接触的N +扩散区，与N阱接触的P +扩散区，以及N +和P +扩散区之间的浅沟槽隔离结构。

    DEEP TRENCH BASED FAR SUBCOLLECTOR REACHTHROUGH
    72.
    发明申请
    DEEP TRENCH BASED FAR SUBCOLLECTOR REACHTHROUGH 失效
    深度基础的FAR SUBCOLLECTOR REACHTHROUGH

    公开(公告)号：US20080211064A1

    公开(公告)日：2008-09-04

    申请号：US11680637

    申请日：2007-03-01

    申请人： Bradley A. Orner ,  Robert M. Rassel ,  David C. Sheridan ,  Steven H. Voldman

    发明人： Bradley A. Orner ,  Robert M. Rassel ,  David C. Sheridan ,  Steven H. Voldman

    IPC分类号： H01L29/06 ,  H01L21/425

    CPC分类号： H01L21/763 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/732

    摘要： A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.

    摘要翻译： 通过将掺杂剂离子注入到初始半导体衬底的区域中，随后半导体材料的外延生长，形成位于超过常规离子注入范围的深度的远的子集电极或掩埋掺杂半导体层。 通过从沉积在邻接远子集电极的至少一个深沟槽中的掺杂材料层向外扩散掺杂剂形成远子集电极的到达区域。 穿通区可以形成在至少一个深沟槽周围，或仅在至少一个深沟槽的一侧上。 如果至少一个沟槽的内部电连接到通孔区域，则可以在至少一个沟槽内的掺杂填充材料上形成金属接触。 如果不是，则在与接触区域接触的次级通过区域上形成金属接触。

    Semiconductor structure
    73.
    发明授权
    Semiconductor structure 有权
    半导体结构

    公开(公告)号：US07242071B1

    公开(公告)日：2007-07-10

    申请号：US11382720

    申请日：2006-07-06

    申请人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

    发明人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

    IPC分类号： H01L29/00

    CPC分类号： H01L27/0623 ,  H01L21/823892 ,  H01L27/0921

    摘要： A structure comprises a deep sub-collector buried in a first epitaxial layer and a near sub-collector buried in a second epitaxial layer. The structure further comprises a deep trench isolation structure isolating a region which is substantially above the deep sub-collector, a reach-through structure in contact with the near sub-collector, and a reach-through structure in contact with the deep sub-collector to provide a low-resistance shunt, which prevents COMS latch-up of a device. The method includes forming a merged triple well double epitaxy/double sub-collector structure.

    摘要翻译： 结构包括埋藏在第一外延层中的深子集电极和埋在第二外延层中的近亚集电极。 该结构还包括一个深沟槽隔离结构，该深沟槽隔离结构隔离了深层次集电极基本上方的区域，与近旁集电极接触的通孔结构以及与深子集电极接触的到达结构 以提供低电阻分流器，其防止COMS闩锁装置。 该方法包括形成合并三阱双外延/双子集电极结构。

    Integrated circuit including transistor structure on depleted silicon-on-insulator, related method and design structure
    74.
    发明授权
    Integrated circuit including transistor structure on depleted silicon-on-insulator, related method and design structure 有权
    集成电路包括绝缘体上绝缘体上的晶体管结构，相关方法和设计结构

    公开(公告)号：US09041105B2

    公开(公告)日：2015-05-26

    申请号：US13553947

    申请日：2012-07-20

    申请人： William F. Clark, Jr. ,  Qizhi Liu ,  Robert M. Rassel ,  Yun Shi

    发明人： William F. Clark, Jr. ,  Qizhi Liu ,  Robert M. Rassel ,  Yun Shi

    IPC分类号： H01L27/088 ,  H01L27/12 ,  H01L21/84 ,  H01L21/265

    CPC分类号： H01L27/1203 ,  H01L21/84

    摘要： An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first semiconductor layer disposed on the substrate; a shallow trench isolation (STI) extending through the first semiconductor layer to within a portion of the substrate, the STI substantially separating a first n+ region and a second n+ region; and a gate disposed on a portion of the first semiconductor layer and connected to the STI, the gate including: a buried metal oxide (BOX) layer disposed on the first semiconductor layer and connected to the STI; a cap layer disposed on the BOX layer; and a p-type well component disposed within the first semiconductor layer and the substrate, the p-type well component connected to the second n+ region.

    摘要翻译： 一种集成电路（IC）及其制造方法。 在一个实施例中，IC包括：衬底; 设置在所述基板上的第一半导体层; 在所述衬底的一部分内延伸穿过所述第一半导体层的浅沟槽隔离（STI），所述STI基本上分离第一n +区和第二n +区; 以及设置在所述第一半导体层的与所述STI连接的部分上的栅极，所述栅极包括：设置在所述第一半导体层上并连接到所述STI的掩埋金属氧化物（BOX）层; 设置在BOX层上的盖层; 以及设置在第一半导体层和衬底内的p型阱组件，p型阱组件连接到第二n +区。

    Intralevel conductive light shield
    76.
    发明授权
    Intralevel conductive light shield 有权
    Intralevel导电灯罩

    公开(公告)号：US08709855B2

    公开(公告)日：2014-04-29

    申请号：US12133379

    申请日：2008-06-05

    申请人： Jeffrey P. Gambino ,  Zhong-Xiang He ,  Kevin N. Ogg ,  Richard J. Rassel ,  Robert M. Rassel

    发明人： Jeffrey P. Gambino ,  Zhong-Xiang He ,  Kevin N. Ogg ,  Richard J. Rassel ,  Robert M. Rassel

    IPC分类号： H01L21/00

    CPC分类号： H01L23/552 ,  H01L27/14623 ,  H01L27/14636 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A conductive light shield is formed over a first dielectric layer of a via level in a metal interconnect structure. The conductive light shield is covers a floating drain of an image sensor pixel cell. A second dielectric layer is formed over the conductive light shield and at least one via extending from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive image sensor pixel cell is less prone to noise due to the blockage of light over the floating drain by the conductive light shield.

    摘要翻译： 在金属互连结构中的通孔级的第一介电层上形成导电屏蔽。 导电屏蔽覆盖图像传感器像素单元的浮动漏极。 在导电光屏蔽上形成第二电介质层，并且在金属互连结构中形成有从第二电介质层的顶表面延伸到第一介电层的底表面的至少一个通孔。 导电屏蔽可以形成在半导体衬底的顶表面和第一金属线电平之间的接触电平内，或者可以通过两个金属线电平之间的电平形成在任何金属互连中。 本发明的图像传感器像素单元由于在导电屏蔽层上的浮动漏极上的光阻塞而不容易产生噪声。

    Semiconductor structure including trench capacitor and trench resistor
    80.
    发明授权
    Semiconductor structure including trench capacitor and trench resistor 有权
    半导体结构包括沟槽电容和沟槽电阻

    公开(公告)号：US08110862B2

    公开(公告)日：2012-02-07

    申请号：US12499452

    申请日：2009-07-08

    申请人： Kangguo Cheng ,  Robert M. Rassel

    发明人： Kangguo Cheng ,  Robert M. Rassel

    IPC分类号： H01L29/94 ,  H01L21/283

    CPC分类号： H01L29/945 ,  H01L27/016 ,  H01L27/0682 ,  H01L28/20 ,  H01L29/66181

    摘要： A structure and a method for fabrication of the structure use a capacitor trench for a trench capacitor and a resistor trench for a trench resistor. The structure is typically a semiconductor structure. In a first instance, the capacitor trench has a linewidth dimension narrower than the resistor trench. The trench linewidth difference provides an efficient method for fabricating the trench capacitor and the trench resistor. In a second instance, the trench resistor comprises a conductor material at a periphery of the resistor trench and a resistor material at a central portion of the resistor trench.

    摘要翻译： 用于制造结构的结构和方法使用用于沟槽电容器的电容器沟槽和用于沟槽电阻器的电阻器沟槽。 该结构通常是半导体结构。 在第一种情况下，电容器沟槽的线宽尺寸比电阻器沟槽窄。 沟槽线宽差提供了制造沟槽电容器和沟槽电阻器的有效方法。 在第二种情况下，沟槽电阻器包括在电阻器沟槽的周边处的导体材料和在电阻器沟槽的中心部分处的电阻器材料。