中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

87 records (took 0.018 seconds)

    INTEGRATED CIRCUIT STRUCTURE INCLUDING DEEP N-WELL SELF-ALIGNED WITH STI AND METHOD OF FORMING SAME
    72.
    发明申请
    INTEGRATED CIRCUIT STRUCTURE INCLUDING DEEP N-WELL SELF-ALIGNED WITH STI AND METHOD OF FORMING SAME 审中-公开

    公开(公告)号：US20190088557A1

    公开(公告)日：2019-03-21

    申请号：US15705429

    申请日：2017-09-15

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jagar Singh ,  Jerome J. B. Ciavatti

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08

    Abstract: The disclosure is directed to integrated circuit (IC) structures, and more particularly, to IC structures including a deep n-well that is self-aligned with a shallow trench isolation (STI). The integrated circuit structure may include: a first pair of isolation regions within a substrate; a first region of the substrate between the first pair of isolation regions having a first conductivity type; a second region of the substrate beneath the first pair of isolation regions and the first region of the substrate having a second conductivity type opposite the first conductivity type of the first region of the substrate, wherein the second region of the substrate includes a second pair of isolation regions that are self-aligned with and in contact with the first pair of isolation regions.

    LDMOS finFET structures with multiple gate structures
    73.
    发明授权
    LDMOS finFET structures with multiple gate structures 有权

    公开(公告)号：US10121878B1

    公开(公告)日：2018-11-06

    申请号：US15711415

    申请日：2017-09-21

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jerome Ciavatti ,  Jagar Singh ,  Hui Zang

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L21/441 ,  H01L29/06 ,  H01L21/266

    Abstract: Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second fins are formed on a substrate. A first well of a first conductivity type is arranged partially in the substrate and partially in the first fin. A second well of a second conductivity type is arranged partially in the substrate, partially in the first fin, and partially in the second fin. First and second source/drain regions of the second conductivity type are respectively formed within the first well in the first fin and within the second well in the second fin. Spaced-apart gate structures are formed that overlap with respective portions of the first fin. A doped region of the first conductivity type is arranged within the second well in the first fin between the first and second gate structures.

    Methods of fabricating nanowire structures
    77.
    发明授权
    Methods of fabricating nanowire structures 有权
    制造纳米线结构的方法

    公开(公告)号：US09508795B2

    公开(公告)日：2016-11-29

    申请号：US14613983

    申请日：2015-02-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Chun Yu Wong ,  Min-hwa Chi ,  Ashish Baraskar ,  Jagar Singh

    IPC: H01L21/20 ,  H01L29/06 ,  H01L21/306 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66

    CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3083 ,  H01L21/31116 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/78696

    Abstract: Methods are presented for fabricating nanowire structures, such as one or more nanowire field effect transistors. The methods include, for instance: providing a substrate and forming a fin above the substrate so that the fin has a first sidewall including one or more elongate first sidewall protrusions and a second sidewall including one or more elongate second sidewall protrusions, with the one or more elongate second sidewall protrusions being substantially aligned with the one or more elongate first sidewall protrusions; and, anisotropically etching the fin with the elongate first sidewall protrusions and the elongate second sidewall protrusions to define the one or more nanowires. The etchant may be chosen to selectively etch along a pre-defined crystallographic plane, such as the (111) crystallographic plane, to form the nanowire structures.

    Abstract translation: 提出了用于制造纳米线结构的方法，例如一个或多个纳米线场效应晶体管。 所述方法包括例如：提供衬底并在衬底上形成翅片，使得翅片具有包括一个或多个细长的第一侧壁突出部的第一侧壁和包括一个或多个细长的第二侧壁突出部的第二侧壁， 更细长的第二侧壁突起基本上与一个或多个细长的第一侧壁突起对准; 并且用细长的第一侧壁突起和细长的第二侧壁突起各向异性地蚀刻翅片以限定一个或多个纳米线。 可以选择蚀刻剂以沿着预定义的结晶平面（例如（111）晶面）选择性地蚀刻，以形成纳米线结构。

    Devices and methods of forming higher tunability FinFET varactor
    79.
    发明授权
    Devices and methods of forming higher tunability FinFET varactor 有权
    形成较高可调谐性FinFET变容二极管的器件和方法

    公开(公告)号：US09437713B2

    公开(公告)日：2016-09-06

    申请号：US14181790

    申请日：2014-02-17

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jagar Singh ,  Andy Wei ,  Gopal Srinivasan ,  Amaury Gendron

    IPC: H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L29/94 ,  H01L27/06

    CPC classification number: H01L29/66795 ,  H01L21/3086 ,  H01L27/0629 ,  H01L29/785 ,  H01L29/94

    Abstract: Devices and methods for forming semiconductor devices with wider FinFETs for higher tunability of the varactor are provided. One method includes, for instance: obtaining an intermediate semiconductor device; applying a spacer layer over the semiconductor device; etching the semiconductor device to remove at least a portion of the spacer layer to expose the plurality of mandrels; removing the mandrels; etching the semiconductor device to remove a portion of the dielectric layer; forming at least one fin; and removing the spacer layer and the dielectric layer. One intermediate semiconductor device includes, for instance: a substrate; a dielectric layer over the substrate; a plurality of mandrels formed on the dielectric layer, the mandrels including a first set of mandrels and a second set of mandrels, wherein the first set of mandrels have a width twice as large as the second set of mandrels; and a spacer layer applied over the mandrels.

    Abstract translation: 提供了用于形成具有更宽FinFET的半导体器件以用于变容二极管的较高可调性的装置和方法。 一种方法包括，例如：获得中间半导体器件; 在所述半导体器件上施加间隔层; 蚀刻半导体器件以去除间隔层的至少一部分以暴露多个心轴; 去除心轴; 蚀刻半导体器件以去除电介质层的一部分; 形成至少一个翅片; 以及去除间隔层和电介质层。 一个中间半导体器件包括例如：衬底; 介电层; 形成在所述电介质层上的多个心轴，所述心轴包括第一组心轴和第二组心轴，其中所述第一组心轴的宽度是所述第二组心轴的两倍; 以及施加在心轴上的间隔层。

Patent Agency Ranking