公开(公告)号：US20120279952A1

公开(公告)日：2012-11-08

申请号：US13101322

申请日：2011-05-05

申请人： Gian Pietro Vanalli ,  Stefano Corno ,  Giovanni Campardo ,  Angelo Visconti ,  Silvia Beltrami ,  Alexey Petrushin

发明人： Gian Pietro Vanalli ,  Stefano Corno ,  Giovanni Campardo ,  Angelo Visconti ,  Silvia Beltrami ,  Alexey Petrushin

IPC分类号： H05B3/00

CPC分类号： G11C16/26 ,  G11C11/00 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3431 ,  H01L23/345 ,  H01L2924/0002 ,  H05B3/00 ,  H01L2924/00

摘要： A memory controller can provide current to a heater in a flash memory to reduce cycling induced errors. If necessary, after heating, the memory may be refreshed. In non-battery powered systems, data may be removed from the memory prior to heating and restored to the memory after heating.

摘要翻译： 存储器控制器可以向闪存中的加热器提供电流以减少循环引起的误差。 如果需要，加热后，可以刷新存储器。 在非电池供电系统中，数据可能在加热之前从存储器中移除，并在加热后恢复到存储器。

公开(公告)号：US06304490B1

公开(公告)日：2001-10-16

申请号：US09675985

申请日：2000-09-29

申请人： Giovanni Campardo ,  Stefano Zanardi ,  Maurizio Branchetti ,  Stefano Ghezzi

发明人： Giovanni Campardo ,  Stefano Zanardi ,  Maurizio Branchetti ,  Stefano Ghezzi

IPC分类号： G11C1134

CPC分类号： H01L27/115 ,  G05F3/205

摘要： A biasing device for biasing a memory cell having a substrate bias terminal associated therewith. The biasing device includes a first sub-threshold circuitry block adapted to supply an appropriate current during the device standby phase through a restore transistor connected between a supply voltage reference and the substrate bias terminal of the memory cell, and having a control terminal connected to a bias circuit, in turn connected between the supply voltage reference and a ground voltage reference to drive the restore transistor with a current of limited value. The device further includes a second feedback block for fast charging the substrate bias terminal, being connected between the supply voltage reference and the ground voltage reference and comprising a first bias transistor having a control terminal connected to the ground voltage reference via a stabilization transistor, having in turn a control terminal connected to an output node, and to the control terminal of a first regulation transistor connected between the supply voltage reference and the ground voltage reference, the stabilization transistor and first regulation transistor providing feedback for the bias transistor, thereby to restrict the voltage range of the output node.

摘要翻译： 一种用于偏置具有与其相关联的衬底偏置端子的存储单元的偏置装置。 偏置装置包括第一子阈值电路块，其适于在器件待机阶段期间通过连接在电源电压基准和存储单元的衬底偏置端之间的恢复晶体管提供适当的电流，并且具有连接到存储器单元的控制端 偏置电路又连接在电源参考电压和地电压基准之间，以有限的电流驱动恢复晶体管。 该装置还包括用于对衬底偏置端子进行快速充电的第二反馈块，其连接在电源电压基准和接地电压基准之间，并且包括具有经由稳定晶体管连接到接地电压基准的控制端的第一偏置晶体管， 连接到输出节点的控制终端，以及连接在电源电压基准和接地电压基准之间的第一调节晶体管的控制端，稳压晶体管和第一调节晶体管为偏置晶体管提供反馈，从而限制 输出节点的电压范围。

公开(公告)号：US6150844A

公开(公告)日：2000-11-21

申请号：US898811

申请日：1997-07-23

申请人： Giovanni Campardo ,  Stefano Zanardi ,  Carla Golla

发明人： Giovanni Campardo ,  Stefano Zanardi ,  Carla Golla

IPC分类号： H03K19/003 ,  H03K19/0175 ,  H03K19/02 ,  H03L5/00

CPC分类号： H03K19/00315 ,  H03K19/00384

摘要： An output stage for electronic circuits with high voltage tolerance and of the type comprising an output buffer made up of a complementary transistor pair comprising a P-channel MOS pull-up transistor and an N-channel MOS pull-down transistor. The transistors are connected together to make up an output terminal of the stage which comprises in addition a switch having an input connected to the output terminal of the stage and an output connected to the control terminal of the pull-up transistor to drive said control terminal in a state of extinction of the output buffer.

摘要翻译： 一种用于具有高电压容限的电子电路的输出级，其类型包括由包括P沟道MOS上拉晶体管和N沟道MOS下拉晶体管的互补晶体管对构成的输出缓冲器。 晶体管连接在一起以构成电平的输出端，另外还包括具有连接到电平的输出端的输入的开关和连接到上拉晶体管的控制端的输出，以驱动所述控制端 处于输出缓冲区的灭绝状态。

公开(公告)号：US5949713A

公开(公告)日：1999-09-07

申请号：US94916

申请日：1998-06-15

申请人： Lorenzo Bedarida ,  Giovanni Campardo ,  Giuseppe Fusillo ,  Andrea Silvagni

发明人： Lorenzo Bedarida ,  Giovanni Campardo ,  Giuseppe Fusillo ,  Andrea Silvagni

IPC分类号： G11C8/12 ,  G11C16/08 ,  G11C11/34

CPC分类号： G11C8/12 ,  G11C16/08

摘要： A memory array is divided, at the design stage, into a plurality of elementary sectors; depending on the specific application and the requirements of the user, the elementary sectors are grouped into composite sectors of desired size and number; a correlating unit memorizes the correlation between each composite sector and the elementary sectors; and, to address a composite sector, the relative address is supplied to the correlating unit which provides for addressing the elementary sectors associated with the addressed composite sector on the basis of the memorized correlation table.

摘要翻译： 存储器阵列在设计阶段被划分成多个基本扇区; 取决于用户的具体应用和要求，基本扇区被分组成所需大小和数量的复合扇区; 相关单元记录每个复合扇区与基本扇区之间的相关性; 并且为了寻址复合扇区，将相对地址提供给相关单元，该相关单元基于存储的相关表来提供与寻址的复合扇区相关联的基本扇区的寻址。

公开(公告)号：US5923076A

公开(公告)日：1999-07-13

申请号：US811577

申请日：1997-03-05

申请人： Giovanni Campardo ,  Matteo Zammattio ,  Stefano Ghezzi

发明人： Giovanni Campardo ,  Matteo Zammattio ,  Stefano Ghezzi

IPC分类号： H01L23/485 ,  H01L29/78

CPC分类号： H01L24/02 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107

摘要： An integrated device having an N-type well region formed in a P-type substrate and an N.sup.+ type contact ring housed in the well region. The well region forms respective capacitors with a conductive layer superimposed on the substrate, and with the substrate itself. The conductive layer and the substrate are grounded, and the contact ring is connected to the supply, so that the two capacitors are in parallel to each other and, together with the internal resistance of the well region, form a filter for stabilizing the supply voltage. When connected to an input buffer stage of the device, the filter provides for damping the peaks produced on the supply line of the input buffer by high-current switching of the output buffers.

摘要翻译： 具有形成在P型衬底中的N型阱区和容纳在阱区中的N +型接触环的集成器件。 阱区形成具有叠加在衬底上的导电层以及衬底本身的各个电容器。 导电层和基板接地，接触环连接到电源，使得两个电容器彼此平行，并且与阱区域的内部电阻一起形成用于稳定电源电压的滤波器 。 当连接到器件的输入缓冲级时，滤波器通过输出缓冲器的高电流切换来提供阻尼输入缓冲器电源线上产生的峰值。

公开(公告)号：US5778012A

公开(公告)日：1998-07-07

申请号：US671848

申请日：1996-06-28

申请人： Maurizio Branchetti ,  Carla Golla ,  Giovanni Campardo

发明人： Maurizio Branchetti ,  Carla Golla ,  Giovanni Campardo

IPC分类号： G06F11/10 ,  G11C29/00

CPC分类号： G06F11/1008

摘要： A memory device including first and second memory cell arrays in which are stored respectively user data and error identification and correction data. The memory device also includes first and second decoding means operationally connected to the first and the second memory cell arrays for producing select user data signals and select error identification and correction data signals. The memory device further includes error identification means operationally coupled to the first and the second decoding means. The memory device also comprises error correction means operationally connected to the first and the second decoding means and to the error identification means. Finally the memory device includes a control unit operationally connected to the second decoding means, to the error identification means and to the error correction means to enable the second decoding means and the error correction means if the error identification means detect an error in the select user data signals.

摘要翻译： 一种包括第一和第二存储单元阵列的存储器件，其中分别存储有用户数据和错误识别和校正数据。 存储装置还包括第一和第二解码装置，可操作地连接到第一和第二存储单元阵列，用于产生选择用户数据信号并选择误差识别和校正数据信号。 存储器装置还包括可操作地耦合到第一和第二解码装置的错误识别装置。 存储装置还包括可操作地连接到第一和第二解码装置和错误识别装置的纠错装置。 最后，存储装置包括操作地连接到第二解码装置的控制单元，如果错误识别装置检测到选择用户中的错误，则错误识别装置和错误校正装置启用第二解码装置和纠错装置 数据信号。

公开(公告)号：US5587946A

公开(公告)日：1996-12-24

申请号：US212907

申请日：1994-03-15

申请人： Giovanni Campardo ,  Giuseppe Crisenza ,  Marco Dallabora

发明人： Giovanni Campardo ,  Giuseppe Crisenza ,  Marco Dallabora

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  G11C16/02

CPC分类号： G11C16/04 ,  G11C16/0416 ,  G11C16/30

摘要： To reduce read and write errors caused by depleted memory array cells being turned on even when not selected, the nonselected memory cells are so biased as to present a floating terminal and a terminal at a positive voltage with respect to the substrate region. The threshold voltage of nonselected cells (i.e., the minimum voltage between the gate and source terminals for the cell to be turned on) increases due to a "body effect", whereby the threshold voltage depends on the voltage drop between the source terminal and the substrate. The source line of a selected cell is biased to a positive value greater than that of the bit line of the selected cell. Methods for reading, writing and erasing cells using certain voltage levels are disclosed.

摘要翻译： 为了减少由于耗尽的存储器阵列单元即使未被选择而导通的读取和写入错误，非选择的存储器单元被偏置以使浮动端子和端子相对于衬底区域处于正电压。 非选择单元的阈值电压（即，用于导通的单元的栅极和源极端子之间的最小电压）由于“体效应”而增加，由此阈值电压取决于源极端子与源极端子之间的电压降 基质。 所选单元格的源极线被偏置为大于所选单元的位线的正值。 公开了使用特定电压电平读取，写入和擦除单元的方法。

公开(公告)号：US08228684B2

公开(公告)日：2012-07-24

申请号：US12116852

申请日：2008-05-07

申请人： Aldo Losavio ,  Giovanni Campardo ,  Stefano Ricciardi

发明人： Aldo Losavio ,  Giovanni Campardo ,  Stefano Ricciardi

IPC分类号： H05K1/11 ,  H05K1/14

CPC分类号： H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06596 ,  H01L2924/01019 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electronic system adapted to perform a corresponding function and including at least a first subsystem and a second subsystem, the first subsystem and the second subsystem being operatively couplable to each other through a plurality of electric connections to perform the function of the system, in which the first subsystem and the second subsystem are respectively integrated on a first material chip and on a second material chip, the plurality of electric connections including a plurality of conductive through holes formed in at least one of the first and second chips and adapted to form a corresponding plurality of inter-chip electric connections when the first and the second chips are superimposed.

摘要翻译： 一种适于执行相应功能并且至少包括第一子系统和第二子系统的电子系统，所述第一子系统和所述第二子系统通过多个电连接可操作地彼此耦合以执行所述系统的功能，其中 第一子系统和第二子系统分别集成在第一材料芯片上并且在第二材料芯片上，多个电连接包括形成在第一和第二芯片中的至少一个芯片中的多个导电通孔，并且适于形成 当第一和第二芯片叠加时相应的多个芯片间电连接。

公开(公告)号：US20110307762A1

公开(公告)日：2011-12-15

申请号：US13122909

申请日：2008-10-09

申请人： Federico Tiziani ,  Giovanni Campardo ,  Massimo Iaculo ,  Claudio Giaccio ,  Manuela Scognamiglio ,  Danilo Caraccio ,  Ornella Vitale ,  Antonino Pollio

发明人： Federico Tiziani ,  Giovanni Campardo ,  Massimo Iaculo ,  Claudio Giaccio ,  Manuela Scognamiglio ,  Danilo Caraccio ,  Ornella Vitale ,  Antonino Pollio

IPC分类号： G06F11/10 ,  G06F12/02

CPC分类号： G06F3/0625 ,  G06F1/3275 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246 ,  G06F13/1668 ,  G11C29/52 ,  Y02D10/14

摘要： A single virtualized ECC NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack.

摘要翻译： 单个虚拟化ECC NAND控制器执行ECC算法并管理NAND闪存堆栈。 虚拟化ECC NAND控制器允许主机处理器作为单个NAND芯片驱动闪存器件堆叠，同时控制器将数据重定向到堆栈中选择的NAND存储器件。

公开(公告)号：US20060250847A1

公开(公告)日：2006-11-09

申请号：US11401521

申请日：2006-04-11

申请人： Giovanni Campardo

发明人： Giovanni Campardo

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/0433 ,  G11C16/26

摘要： A non-volatile electronic memory device may be monolithically integrated on a semiconductor and be of the Flash EEPROM type having a NAND architecture and including at least one memory matrix organized in rows and columns of memory cells. Advantageously, the matrix may include at least one portion having a different data storage capacity and a different access speed than another portion.

摘要翻译： 非易失性电子存储器件可以单片地集成在半导体上，并且具有具有NAND架构并且包括以存储器单元的行和列组织的至少一个存储器矩阵的闪存EEPROM类型。 有利地，矩阵可以包括具有与另一部分不同的数据存储容量和不同访问速度的至少一个部分。