利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

96 条记录 (耗时 0.021 秒)

    INTERFACE BOARD OF A TESTING HEAD FOR A TEST EQUIPMENT OF ELECTRONIC DEVICES AND CORRESPONDING PROBE HEAD
    2.
    发明申请
    INTERFACE BOARD OF A TESTING HEAD FOR A TEST EQUIPMENT OF ELECTRONIC DEVICES AND CORRESPONDING PROBE HEAD 有权
    用于电子设备测试设备和相关探头的测试头接口板

    公开(公告)号：US20140015560A1

    公开(公告)日：2014-01-16

    申请号：US13548004

    申请日：2012-07-12

    申请人： Giovanni Campardo ,  Flavio Maggioni ,  Riccardo Liberini

    发明人： Giovanni Campardo ,  Flavio Maggioni ,  Riccardo Liberini

    IPC分类号： G01R1/073

    CPC分类号： G01R1/07378

    摘要： An interface board of a testing head for a test equipment of electronic devices is described. The testing head includes a plurality of contact probes, each contact probe having at least one contact tip suitable to abut against contact pads of a device to be tested, as well as a contact element for the connection with a board of the test equipment. Suitably, the interface board comprises a substrate and at least one redirecting die housed on a first surface of that substrate and a plurality of contact pins projecting from a second surface of that substrate opposed to the first surface. The redirecting die includes at least one semiconductor substrate whereon at least a first plurality of contact pads is realized, suitable to contact a contact element of a contact probe of the testing head, the contact pins being suitable to contact the board.

    摘要翻译： 描述了用于电子设备的测试设备的测试头的接口板。 测试头包括多个接触探针，每个接触探针具有至少一个适于邻接待测试装置的接触垫的接触尖端，以及用于与测试设备的板连接的接触元件。 适当地，接口板包括衬底和容纳在该衬底的第一表面上的至少一个重定向模具和从该衬底的与第一表面相对的第二表面突出的多个接触针。 重定向管芯包括至少一个半导体衬底，其中至少第一多个接触焊盘被实现，适于接触测试头的接触探针的接触元件，接触针适于接触该板。

    ERROR CORRECTING CODES FOR INCREASED STORAGE CAPACITY IN MULTILEVEL MEMORY DEVICES
    4.
    发明申请
    ERROR CORRECTING CODES FOR INCREASED STORAGE CAPACITY IN MULTILEVEL MEMORY DEVICES 有权
    在多个存储器件中增加存储容量的错误校正代码

    公开(公告)号：US20100318877A1

    公开(公告)日：2010-12-16

    申请号：US12482400

    申请日：2009-06-10

    申请人： Paolo Amato ,  Giovanni Campardo

    发明人： Paolo Amato ,  Giovanni Campardo

    IPC分类号： H03M13/29 ,  H03M13/11 ,  G06F11/10

    CPC分类号： H03M13/05 ,  G11C2029/0411 ,  H03M13/15 ,  H03M13/152 ,  H03M13/256 ,  H03M13/27 ,  H03M13/29 ,  H03M13/2933 ,  H03M13/2936 ,  H03M13/41

    摘要： Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, data may be programmed and/or read from a matrix of nonvolatile memory cells with concatenated encoding/decoding schemes. In some embodiments, a calculation module may determine an actual bit per cell value of a given combination of parameters of a nonvolatile memory device. Still other embodiments may be described and claimed.

    摘要翻译： 本公开的实施例提供了与具有纠错的多级编码相关的方法，系统和装置。 在一些实施例中，可以使用级联的编码/解码方案从非易失性存储器单元的矩阵中编程和/或读取数据。 在一些实施例中，计算模块可以确定非易失性存储器件的给定参数组合的每个单元值的实际位数。 可以描述和要求保护其他实施例。

    Voltage regulator or non-volatile memories implemented with low-voltage transistors
    5.
    发明授权
    Voltage regulator or non-volatile memories implemented with low-voltage transistors 有权
    用低压晶体管实现的稳压器或非易失性存储器

    公开(公告)号：US07777466B2

    公开(公告)日：2010-08-17

    申请号：US11844470

    申请日：2007-08-24

    申请人： Luca Crippa ,  Giancarlo Ragone ,  Miriam Sangalli ,  Giovanni Campardo ,  Rino Micheloni

    发明人： Luca Crippa ,  Giancarlo Ragone ,  Miriam Sangalli ,  Giovanni Campardo ,  Rino Micheloni

    IPC分类号： G05F1/40

    CPC分类号： G11C5/147 ,  G05F1/565 ,  G11C16/30

    摘要： A voltage regulator integrated in a chip of semiconductor material is provided. The regulator has a first input terminal for receiving a first voltage and an output terminal for providing a regulated voltage being obtained from the first voltage, the regulator including: a differential amplifier for receiving a comparison voltage and a feedback signal being a function of the regulated voltage, and for proving a regulation signal according to a comparison between the comparison voltage and the feedback signal, the differential amplifier having a first supply terminal being coupled with a reference terminal for receiving a reference voltage and a second supply terminal, a regulation transistor having a control terminal for receiving the regulation signal, and a conduction first terminal and a conduction second terminal being coupled through loading means between the reference terminal and the first input terminal of the regulator, the second terminal of the regulation transistor being coupled with the output terminal of the regulator, wherein the second supply terminal of the differential amplifier is coupled with a second input terminal of the regulator for receiving a second voltage being lower than the first voltage in absolute value, and wherein the regulator further includes a set of auxiliary transistors being connected in series between the second terminal of the regulation transistor and the output terminal of the regulator, and control means for controlling the auxiliary transistors according to the regulated voltage.

    摘要翻译： 提供集成在半导体材料芯片中的电压调节器。 所述调节器具有用于接收第一电压的第一输入端子和用于提供从所述第一电压获得的调节电压的输出端子，所述调节器包括：用于接收比较电压的差分放大器和作为所述第一电压的函数的反馈信号 电压，并且为了根据比较电压和反馈信号之间的比较来证明调节信号，差分放大器具有与用于接收参考电压的参考端子耦合的第一电源端子和第二电源端子，调节晶体管具有 用于接收所述调节信号的控制端子，以及通过所述参考端子和所述调节器的所述第一输入端子之间的负载装置耦合的导通第一端子和导通第二端子，所述调节晶体管的所述第二端子与所述输出端子 的调节器，其中第二电源 差分放大器的nal与调节器的第二输入端耦合，用于接收低于绝对值中的第一电压的第二电压，并且其中调节器还包括一组辅助晶体管，串联连接在第二端 调节器的调节晶体管和输出端子，以及用于根据调节电压控制辅助晶体管的控制装置。

    MULTI CHIP ELECTRONIC SYSTEM
    7.
    发明申请
    MULTI CHIP ELECTRONIC SYSTEM 有权
    多芯片电子系统

    公开(公告)号：US20080278923A1

    公开(公告)日：2008-11-13

    申请号：US12116852

    申请日：2008-05-07

    申请人： Aldo Losavio ,  Giovanni Campardo ,  Stefano Ricciardi

    发明人： Aldo Losavio ,  Giovanni Campardo ,  Stefano Ricciardi

    IPC分类号： H05K1/14

    CPC分类号： H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06596 ,  H01L2924/01019 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

    摘要： An electronic system adapted to perform a corresponding function and including at least a first subsystem and a second subsystem, the first subsystem and the second subsystem being operatively couplable to each other through a plurality of electric connections to perform the function of the system, in which the first subsystem and the second subsystem are respectively integrated on a first material chip and on a second material chip, the plurality of electric connections including a plurality of conductive through holes formed in at least one of the first and second chips and adapted to form a corresponding plurality of inter-chip electric connections when the first and the second chips are superimposed.

    摘要翻译： 一种适于执行相应功能并且至少包括第一子系统和第二子系统的电子系统，所述第一子系统和所述第二子系统通过多个电连接可操作地彼此耦合以执行所述系统的功能，其中 第一子系统和第二子系统分别集成在第一材料芯片上并且在第二材料芯片上，多个电连接包括形成在第一和第二芯片中的至少一个芯片中的多个导电通孔，并且适于形成 当第一和第二芯片叠加时相应的多个芯片间电连接。

    Semiconductor memory with embedded DRAM
    8.
    发明授权
    Semiconductor memory with embedded DRAM 失效
    具有嵌入式DRAM的半导体存储器

    公开(公告)号：US07027317B2

    公开(公告)日：2006-04-11

    申请号：US10720013

    申请日：2003-11-20

    申请人： Giovanni Campardo ,  Rino Micheloni

    发明人： Giovanni Campardo ,  Rino Micheloni

    IPC分类号： G11C11/24 ,  G11C14/00

    CPC分类号： G11C11/005

    摘要： A semiconductor memory comprises a plurality of memory cells, for example Flash memory cells, arranged in a plurality of lines, and a plurality of memory cell access signal lines, each one associated with at least one respective line of memory cells, for accessing the memory cells of the at least one respective line of memory cells; each signal line has a capacitance intrinsically associated therewith. A plurality of volatile memory cells is provided, each having a capacitive storage element. Each volatile memory cell is associated with a respective signal line, and the respective capacitive storage element formed by the capacitance intrinsically associated with the respective signal lines. In particular, the parasitic capacitances associated with bit lines of a matrix of memory cells can be exploited as capacitive storage elements.

    摘要翻译： 半导体存储器包括多个存储器单元，例如布置在多个行中的闪存单元，以及多个存储单元存取信号线，每个存储单元接入信号线与至少一个相应行的存储单元相关联，用于访问存储器 存储单元的至少一个相应行的单元; 每个信号线具有与其固有相关的电容。 提供了多个易失性存储单元，每个易失性存储单元具有电容存储元件。 每个易失性存储器单元与相应的信号线相关联，并且由与各个信号线固有相关联的电容形成的相应电容存储元件。 特别地，与存储器单元的矩阵的位线相关联的寄生电容可以被用作电容性存储元件。

    Read circuit for a nonvolatile memory
    9.
    发明授权
    Read circuit for a nonvolatile memory 有权
    读取非易失性存储器的电路

    公开(公告)号：US06327184B1

    公开(公告)日：2001-12-04

    申请号：US09621019

    申请日：2000-07-21

    申请人： Rino Micheloni ,  Giovanni Campardo ,  Luca Crippa

    发明人： Rino Micheloni ,  Giovanni Campardo ,  Luca Crippa

    IPC分类号： G11C1606

    CPC分类号： G11C16/28

    摘要： The read circuit comprises an array branch having an input array node connected, via an array bit line, to an array cell; a reference branch having an input reference node connected, via a reference bit line, to a reference cell; a current-to-voltage converter connected to an output array node of the array branch and to an output reference node of the reference branch to supply on the output array node and the output reference node the respective electric potentials correlated to the currents flowing in the array memory cell and, respectively, in the reference memory cell; and a comparator connected at input to the output array node and output reference node and supplying as output a signal indicative of the contents stored in the array memory cell; and an array decoupling stage arranged between the input array node and the output array node to decouple the electric potentials of the input and output array nodes from one another.

    摘要翻译： 读取电路包括具有通过阵列位线连接到阵列单元的输入阵列节点的阵列分支; 参考分支，其具有通过参考位线连接到参考单元的输入参考节点; 连接到阵列分支的输出阵列节点和参考分支的输出参考节点的电流 - 电压转换器，以在输出阵列节点和输出参考节点上提供与在 阵列存储单元，分别在参考存储单元中; 以及比较器，其输入端连接到所述输出阵列节点和输出参考节点，并且作为输出提供指示存储在所述阵列存储单元中的内容的信号; 以及布置在输入阵列节点和输出阵列节点之间的阵列解耦级，以将输入和输出阵列节点的电位彼此去耦。

    Method and a related circuit for adjusting the duration of a synchronization signal ATD for timing the access to a non-volatile memory
    10.
    发明授权
    Method and a related circuit for adjusting the duration of a synchronization signal ATD for timing the access to a non-volatile memory 有权
    方法和相关电路，用于调整同步信号ATD的持续时间，用于定时访问非易失性存储器

    公开(公告)号：US06237104B1

    公开(公告)日：2001-05-22

    申请号：US09222070

    申请日：1998-12-29

    申请人： Rino Micheloni ,  Giovanni Campardo ,  Stefano Commodaro ,  Guido Lomazzi

    发明人： Rino Micheloni ,  Giovanni Campardo ,  Stefano Commodaro ,  Guido Lomazzi

    IPC分类号： G06F1200

    CPC分类号： G11C8/18 ,  G11C16/32

    摘要： A method and related circuit for adjusting the duration of a pulse synchronization signal for the reading phase of memory cells in electronic memory devices which are integrated on semiconductors are discussed. The pulse synchronization signal is produced by a pulse generator when it detects a logical state commutation on at least one input terminal of a plurality of addressing input terminals of the memory cells. The method produces a logical sum between the signal produced by the generator and a pulse signal having a predetermined duration. The logical sum is used to start up the reading phase.

    摘要翻译： 讨论了用于调整集成在半导体上的电子存储器件中的存储器单元的读取阶段的脉冲同步信号的持续时间的方法和相关电路。 当脉冲同步信号检测到存储器单元的多个寻址输入端的至少一个输入端上的逻辑状态换向时，脉冲同步信号由脉冲发生器产生。 该方法产生由发生器产生的信号与具有预定持续时间的脉冲信号之间的逻辑和。 逻辑和用于启动读取阶段。