公开(公告)号：US08552828B1

公开(公告)日：2013-10-08

申请号：US13607295

申请日：2012-09-07

Applicant: Gottfried Beer ,  Urs Elrod ,  Christiane Brunner ,  Thomas Kilger

Inventor： Gottfried Beer ,  Urs Elrod ,  Christiane Brunner ,  Thomas Kilger

IPC: H01F27/29 ,  H01F27/28 ,  H01F5/00

CPC classification number: H01F27/2804 ,  H01F41/041 ,  H01F2027/2819 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/645 ,  H01L24/19 ,  H01L2224/12105 ,  Y10T29/4902 ,  Y10T29/49071

Abstract: In accordance with an embodiment, a transformer includes a first coil disposed in a first conductive layer on a first side of a first dielectric layer, and a second coil disposed in a second conductive layer on a second side of the first dielectric layer. Each coil has a first end disposed inside its respective coil and a second end disposed at an outer perimeter of its respective coil. A first crossover disposed in the second conductive layer is directly connected to the first end of the first coil and extends past the outer perimeter of the first coil. In addition, a second crossover disposed in the first conductive layer is directly connected to the first end of the second coil and extends past the outer perimeter of the second coil.

公开(公告)号：US08492200B2

公开(公告)日：2013-07-23

申请号：US13529315

申请日：2012-06-21

Applicant: Gottfried Beer ,  Irmgard Escher-Poeppel

Inventor： Gottfried Beer ,  Irmgard Escher-Poeppel

IPC: H01L21/00

CPC classification number: H01L24/96 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76879 ,  H01L23/3128 ,  H01L24/18 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/2919 ,  H01L2224/83856 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.

Abstract translation: 公开了一种制造半导体芯片模块和半导体芯片封装的方法。 一个实施例提供第一层，第二层和基层。 第一层设置在基层上，第二层设置在第一层上。 多个半导体芯片被施加在第二层上方，并且具有施加的半导体芯片的第二层与第一层分离。

公开(公告)号：US08431063B2

公开(公告)日：2013-04-30

申请号：US11581060

申请日：2006-10-16

Applicant: Gottfried Beer ,  Markus Brunnbauer ,  Edward Fuergut

Inventor： Gottfried Beer ,  Markus Brunnbauer ,  Edward Fuergut

IPC: B29B17/00

CPC classification number: H01L21/561 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/92 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/96 ,  H01L2224/82

Abstract: A heat treatment method is provided for a panel. The panel includes a plastic housing composition, in which semiconductor chips are embedded by their rear sides and edge sides, and the top sides of the semiconductor chips form a coplanar area with the plastic housing composition. The panel is fixed by its underside on a holder, and a temperature gradient (ΔT) is then generated between top side and the underside of the panel. The temperature gradient (ΔT) is then maintained for at least one delimited or selected time period. The panel is then cooled to room temperature (TR).

Abstract translation: 为面板提供热处理方法。 面板包括塑料外壳组合物，其中半导体芯片由其后侧和边缘侧嵌入，并且半导体芯片的顶侧与塑料外壳组合物形成共面区域。 面板通过其下侧固定在支架上，然后在面板的顶侧和底面之间产生温度梯度（DeltaT）。 然后将温度梯度（DeltaT）保持至少一个定界或选定的时间段。 然后将面板冷却至室温（TR）。

公开(公告)号：US08415803B2

公开(公告)日：2013-04-09

申请号：US12871939

申请日：2010-08-31

Applicant: Thorsten Meyer ,  Gottfried Beer ,  Christian Geissler ,  Thomas Ort ,  Klaus Pressel ,  Bernd Waidhas ,  Andreas Wolter

Inventor： Thorsten Meyer ,  Gottfried Beer ,  Christian Geissler ,  Thomas Ort ,  Klaus Pressel ,  Bernd Waidhas ,  Andreas Wolter

IPC: H01L23/48 ,  H01L21/768

Abstract: A method and a system for routing electrical connections are disclosed. A semiconductor device includes a first semiconductor chip and a routing plane having a plurality of routing lines. A first connecting line is electrically coupled to the first semiconductor chip and one of the plurality of routing lines and a second connecting line is electrically coupled to the one of the plurality of routing lines and to one of a second semiconductor chip or a first external contact element.

公开(公告)号：US20120287583A1

公开(公告)日：2012-11-15

申请号：US13557774

申请日：2012-07-25

Applicant: Klaus Pressel ,  Gottfried Beer

Inventor： Klaus Pressel ,  Gottfried Beer

IPC: H05K7/02 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/185 ,  H05K3/4644 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic assembly is disclosed. One embodiment includes at least one semiconductor chip and a package structure embedding the semiconductor chip. The package structure includes at least one conducting line extending into an area of the package structure outside of the outline of the chip.

Abstract translation: 公开了一种电子组件。 一个实施例包括至少一个半导体芯片和嵌入半导体芯片的封装结构。 封装结构包括延伸到芯片轮廓外部的封装结构区域中的至少一条导线。

公开(公告)号：US20120258594A1

公开(公告)日：2012-10-11

申请号：US13084105

申请日：2011-04-11

Applicant: Hans-Joachim Barth ,  Jens Pohl ,  Gottfried Beer ,  Heinrich Koerner

Inventor： Hans-Joachim Barth ,  Jens Pohl ,  Gottfried Beer ,  Heinrich Koerner

IPC: H01L21/28

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6688 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.

Abstract translation: 公开了一种片上系统的结构以及片上系统的形成方法。 在一个实施例中，一种制造片上系统的方法包括从衬底的背面形成穿透衬底开口，穿过衬底开口设置在第一和第二区域之间，第一区域包括用于RF电路的装置，第二区域包括第二 区域包括用于其他电路的装置。 该方法还包括在光致抗蚀剂层上形成用于再分配线的图案，设置在背面下方的光致抗蚀剂层，以及用导电材料填充贯通基板开口和再分配线图案。

公开(公告)号：US08237259B2

公开(公告)日：2012-08-07

申请号：US11762411

申请日：2007-06-13

Applicant: Klaus Pressel ,  Gottfried Beer

Inventor： Klaus Pressel ,  Gottfried Beer

IPC: H01L23/053 ,  H01L23/12

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/185 ,  H05K3/4644 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic assembly is disclosed. One embodiment includes at least one semiconductor chip and a package structure embedding the semiconductor chip. The package structure includes at least one conducting line extending into an area of the package structure outside of the outline of the chip. The electronic assembly further includes a substrate embedding the package structure.

Abstract translation: 公开了一种电子组件。 一个实施例包括至少一个半导体芯片和嵌入半导体芯片的封装结构。 封装结构包括延伸到芯片轮廓外部的封装结构区域中的至少一条导线。 电子组件还包括嵌入封装结构的衬底。

公开(公告)号：US08216881B2

公开(公告)日：2012-07-10

申请号：US12947031

申请日：2010-11-16

Applicant: Gottfried Beer ,  Irmgard Escher-Poeppel

Inventor： Gottfried Beer ,  Irmgard Escher-Poeppel

IPC: H01L21/00

CPC classification number: H01L24/96 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76879 ,  H01L23/3128 ,  H01L24/18 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/2919 ,  H01L2224/83856 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.

Abstract translation: 公开了一种制造半导体芯片模块和半导体芯片封装的方法。 一个实施例提供第一层，第二层和基层。 第一层设置在基层上，第二层设置在第一层上。 多个半导体芯片被施加在第二层上方，并且具有施加的半导体芯片的第二层与第一层分离。

公开(公告)号：US08076784B2

公开(公告)日：2011-12-13

申请号：US12904561

申请日：2010-10-14

Applicant: Markus Brunnbauer ,  Recai Sezi ,  Thorsten Meyer ,  Gottfried Beer

Inventor： Markus Brunnbauer ,  Recai Sezi ,  Thorsten Meyer ,  Gottfried Beer

IPC: H01L23/48

CPC classification number: H01L24/96 ,  H01L21/568 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/81

Abstract: Stacked semiconductor chips are disclosed. One embodiment provides a method including a first substrate having a first surface and an opposing second surface. The first substrate includes an array of first connection elements on the first surface of the first substrate. A second substrate has a first surface and an opposing second surface. The second substrate includes an array of second connection elements on the first surface of the second substrate. The first connection elements is attached to the second connection elements; and is thinning at least one of the first substrate and the second substrate after the attachment of the first connection elements to the second connection elements.

Abstract translation: 公开了堆叠的半导体芯片。 一个实施例提供了包括具有第一表面和相对的第二表面的第一基底的方法。 第一衬底包括在第一衬底的第一表面上的第一连接元件的阵列。 第二基板具有第一表面和相对的第二表面。 第二衬底包括在第二衬底的第一表面上的第二连接元件的阵列。 第一连接元件附接到第二连接元件; 并且在将第一连接元件附接到第二连接元件之后使第一基板和第二基板中的至少一个变薄。

公开(公告)号：US20110281405A1

公开(公告)日：2011-11-17

申请号：US13189998

申请日：2011-07-25

Applicant: Gottfried Beer ,  Irmgard Escher-Poeppel

Inventor： Gottfried Beer ,  Irmgard Escher-Poeppel

IPC: H01L21/56

CPC classification number: H01L23/49827 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device and semiconductor device is provided. The method provides a first layer. The first layer includes through-holes. At least one semiconductor chip is provided. The semiconductor chip includes contact elements. The semiconductor chip is placed onto the first layer with the contact elements being aligned with the through-holes. An encapsulant material is applied over the semiconductor chip.

Abstract translation: 提供一种制造半导体器件和半导体器件的方法。 该方法提供第一层。 第一层包括通孔。 提供至少一个半导体芯片。 半导体芯片包括接触元件。 将半导体芯片放置在第一层上，其中接触元件与通孔对齐。 在半导体芯片上施加密封材料。