公开(公告)号：US20060192595A1

公开(公告)日：2006-08-31

申请号：US11360996

申请日：2006-02-24

申请人： Rainer Schnabel ,  Michael Sommer

发明人： Rainer Schnabel ,  Michael Sommer

IPC分类号： G01R19/00

CPC分类号： H01L27/10897 ,  G11C7/065 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/78

摘要： A sense amplifier includes at least two field effect transistors of identical conductivity type, each including a gate terminal, a source terminal, a drain terminal and a bulk terminal. The two field effect transistors are connected such that they are coupled back-to-back between a bit line and a reference line. The bit line is connected to a memory node via a selection transistor. The field effect transistors include bulk or substrate terminals formed in mutually insulated, different wells. The substrate bias voltages and thus the threshold voltages can be set independently via the body effect, so that the threshold voltages that are fundamentally different on account of stochastic effects in the different wells can be adapted to one another. Thus, compensating for the disadvantages that occur in conventional wells, on account of scattering effects during implantation or on account of mechanical stresses which act differently on transistors that are otherwise formed uniformly in the same well.

摘要翻译： 读出放大器包括至少两个具有相同导电类型的场效应晶体管，每个场效应晶体管均包括栅极端子，源极端子，漏极端子和体积端子。 两个场效应晶体管被连接，使得它们在位线和参考线之间背靠背耦合。 位线通过选择晶体管连接到存储器节点。 场效应晶体管包括形成在相互绝缘的不同阱中的体积或衬底端子。 衬底偏置电压以及因此阈值电压可以经由身体效应独立地设定，使得由于不同井中随机效应而根本不同的阈值电压可以彼此适应。 因此，补偿在常规孔中出现的缺点，由于植入过程中的散射效应，或由于另外在同一孔中均匀地形成的晶体管上作用不同的机械应力。

公开(公告)号：US20060060906A1

公开(公告)日：2006-03-23

申请号：US11209548

申请日：2005-08-23

申请人： Michael Sommer

发明人： Michael Sommer

IPC分类号： H01L29/94

CPC分类号： H01L27/10897 ,  Y10S257/908

摘要： A semiconductor memory is disclosed having an electrically conductive region buried in a substrate, and having an array of first and second cells. The first cells are designed as memory cells each having a selection transistor and a storage capacitor and are connected to word lines and first bit lines. The second cells are designed as switchable contacts each having a selection transistor and a resistance element and are connected to a respective one of the word lines and to a second bit line. The resistance element includes a first electrode and a second electrode, which are conductively connected to one another. The second bit line makes it possible to apply a plate voltage to the buried conductive region in low-impedance fashion via the second cells.

公开(公告)号：US20060049862A1

公开(公告)日：2006-03-09

申请号：US11217676

申请日：2005-09-02

申请人： Michael Sommer

发明人： Michael Sommer

IPC分类号： G06F1/04

CPC分类号： H03K5/1252 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  H03K5/084

摘要： An integrated semiconductor memory comprises a clock generator circuit (10), which is driven by an external clock signal (Cext) for the generation of an internal clock signal (Cint). The clock generator circuit (10) generates a level (PI1, PI2) of the internal clock signal if it is driven by the external clock signal with a level (PE1, PE2) for the duration of a sensitivity time (TE). The internal clock signal (Cint) has a higher frequency and phase stability than the external clock signal (Cext). The integrated semiconductor memory furthermore comprises a control circuit (20) for controlling the clock generator circuit (10), which is likewise driven by the external clock signal. The control circuit (20) alters the sensitivity time (TE) of the clock generator circuit (10) in a manner dependent on a frequency of the external clock signal. This prevents a noisy external clock signal (Cext) from leading to an uncontrolled switching behavior of an internal chip logic of the integrated semiconductor memory.

摘要翻译： 集成半导体存储器包括由用于产生内部时钟信号（Cint）的外部时钟信号（Cext）驱动的时钟发生器电路（10）。 时钟发生器电路（10）产生内部时钟信号的电平（PI 1，PI 2），如果它是由具有电平（PE 1，PE 2）的外部时钟信号在灵敏度时间（TE ）。 内部时钟信号（Cint）具有比外部时钟信号（Cext）更高的频率和相位稳定性。 集成半导体存储器还包括用于控制同步由外部时钟信号驱动的时钟发生器电路（10）的控制电路（20）。 控制电路（20）以取决于外部时钟信号的频率的方式改变时钟发生器电路（10）的灵敏度时间（TE）。 这防止噪声外部时钟信号（Cext）导致集成半导体存储器的内部芯片逻辑的不受控制的开关行为。

公开(公告)号：US20050263894A1

公开(公告)日：2005-12-01

申请号：US11127782

申请日：2005-05-12

申请人： Andreas Huber ,  Gunter Gerstmeier ,  Michael Sommer

发明人： Andreas Huber ,  Gunter Gerstmeier ,  Michael Sommer

IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/525

CPC分类号： H01L21/76892

摘要： A metallization surface (5), which acts as an etching stop layer during the production of openings (4) in a passivation layer (3) applied to its upper face and protects an interconnect structure (6) arranged underneath it, is arranged in an uppermost metallization level (1). A further opening is produced in the metal surface (5), through which a focused ion beam is aimed at the interconnect structure (6) in order to connect interconnects to one another and/or to interrupt at least one interconnect. The wiring of the integrated circuit can thus be varied individually, starting from identically produced semiconductor chips.

摘要翻译： 在施加到其上表面的钝化层（3）中制造开口（4）期间用作蚀刻停止层的金属化表面（5）并且保护布置在其下面的互连结构（6）被布置在 最高金属化水平（1）。 在金属表面（5）中产生进一步的开口，通过该开口，聚焦的离子束瞄准互连结构（6），以便将互连件彼此连接和/或中断至少一个互连。 因此，从相同制造的半导体芯片开始，集成电路的布线可以单独变化。

公开(公告)号：US20050156624A1

公开(公告)日：2005-07-21

申请号：US11033988

申请日：2005-01-13

申请人： Michael Sommer

发明人： Michael Sommer

IPC分类号： H03K19/003

CPC分类号： H03K19/00384

摘要： A receiver circuit arrangement contains a receiver circuit (2) having an input (201) for receiving an input signal (IN), having an output (202) for outputting an output signal (OUT_F) and having an inverter circuit (21, 22, 23) having switching transistors (211, 212), to which the input signal is fed, at least one control transistor (221, 222) being connected in series with the switching transistors. A control circuit (3) is connected, on the input side, to a terminal for a reference voltage (VREF) and, on the output side, to the control terminal of the control transistor (221, 222) of the inverter circuit. The control circuit (3) is designed in such a way that the control transistor (221, 222) is driven by the regulating switching circuit in the event of deviations of the reference voltage (VREF) from a voltage value in a reference operating state with a control voltage (VCTL1, VCTL2) that deviates with respect to the reference operating state. The receiver circuit arrangement is comparatively insensitive to fluctuations of a reference voltage with respect to a nominal value of a reference operating state and enables high switching speeds.

摘要翻译： 一种接收器电路装置，包括具有用于接收输入信号（IN）的输入端（201）的接收器电路（2），具有用于输出输出信号（OUT_F）的输出端（202）和具有反相器电路（21,22） 23），其具有输入信号被馈送到的开关晶体管（211,212），与开关晶体管串联连接的至少一个控制晶体管（221,222）。 控制电路（3）在输入侧连接到用于参考电压（VREF）的端子，并且在输出侧连接到逆变器电路的控制晶体管（221,222）的控制端子。 控制电路（3）的设计使得在基准电压（VREF）与参考运行状态的电压值偏差的情况下，控制晶体管（221,222）由调节开关电路驱动， 相对于参考运行状态偏离的控制电压（VCTL 1，VCTL 2）。 接收器电路布置对于参考电压相对于参考运行状态的标称值的波动相对不敏​​感并且能够实现高切换速度。

公开(公告)号：US20050138506A1

公开(公告)日：2005-06-23

申请号：US10949935

申请日：2004-09-24

申请人： Christian Stocken ,  Michael Sommer

发明人： Christian Stocken ,  Michael Sommer

IPC分类号： G11C29/56 ,  G11C5/00 ,  G01R31/28

CPC分类号： G11C29/56 ,  G11C2029/0407 ,  G11C2029/5602

摘要： An apparatus (1) for testing a memory module (2) suitable for exchanging electrical signals with a motherboard (10) contains a device (8a-8k) suitable for detecting the operating state of at least one semiconductor chip (26a-26m) of the module, which device comprises a first set of signal lines (8a-8k), a microcontroller (3) with a memory device (32) for storing the operating state, said microcontroller being electrically connected to the signal lines (8a-8k), a clock generator (5) suitable for generating an operating clock, said clock generator being electrically connected to the microcontroller (3), and a signal connection (13) suitable for communicating a signal for controlling access to the memory module (2) between the circuit board arrangement (10) and the microcontroller (3) and for communicating to the microcontroller (3) a signal for initiating a process of detecting the operating state.

摘要翻译： 一种用于测试适合于与主板（10）交换电信号的存储模块（2）的装置（1），其包含适于检测至少一个半导体芯片（26a- 26m），该装置包括第一组信号线（8a-8k），具有用于存储操作状态的存储器件（32）的微控制器（3），所述微控制器电连接到信号 线路（8a-8k），适于产生工作时钟的时钟发生器（5），所述时钟发生器电连接到微控制器（3），以及信号连接（13），适于传送用于控制访问的信号 到电路板装置（10）和微控制器（3）之间的存储器模块（2）并且用于与微控制器（3）通信用于启动检测操作状态的过程的信号。

公开(公告)号：US20050056873A1

公开(公告)日：2005-03-17

申请号：US10744056

申请日：2003-12-23

申请人： Michael Sommer ,  Gerhard Enders

发明人： Michael Sommer ,  Gerhard Enders

IPC分类号： H01L21/20 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10891 ,  H01L29/66181

摘要： The invention relates to a semiconductor memory, particularly a DRAM, in which the memory cells in each case have a trench capacitor arranged in a lower area of a trench hole and a vertical selection transistor which is formed adjoining an upper area of the trench hole and which connects an inner electrode of the trench capacitor to a bit line, a conductive channel being capable of being formed in dependence on the potential of a word line in the channel area, the channel area completely enclosing the trench hole in its upper area, and the associated word line at least partially enclosing the channel area.

摘要翻译： 本发明涉及一种半导体存储器，特别是DRAM，其中存储单元在每种情况下具有布置在沟槽孔的下部区域中的沟槽电容器和垂直选择晶体管，该垂直选择晶体管形成为邻接沟槽孔的上部区域;以及 其将沟槽电容器的内部电极与位线连接，能够根据沟道区域中的字线的电位形成导电沟道，完全包围其上部区域中的沟槽的沟道区域，以及 相关联的字线至少部分地包围通道区域。

公开(公告)号：US20050040830A1

公开(公告)日：2005-02-24

申请号：US10920204

申请日：2004-08-18

申请人： Fabien Funfrock ,  Michael Sommer

发明人： Fabien Funfrock ,  Michael Sommer

IPC分类号： G01R31/28 ,  G11C29/48 ,  G11C29/56 ,  G01R27/02

CPC分类号： G11C29/56 ,  G01R31/2884 ,  G11C11/401 ,  G11C29/48 ,  G11C2029/5602

摘要： An integrated circuit includes a first circuit component, a second circuit component, and an external terminal for making contact with the circuit. The first circuit component is connected to the external terminal via the second component. A bridging circuit connects the first circuit component to the external terminal and can be activated by a test mode signal. In the active state, the bridging circuit connects the external terminal to the first circuit component while bridging the second circuit component, while it is nonconducting in the deactivated state. Circuit components integrated in the semiconductor chip can be electrically measured nondestructively via activatable switches. Circuit components that lie between the external terminal and the device to be measured can be excluded from the measurement by bridging circuits. The method also makes it possible to measure a plurality of integrated devices in parallel or serially.

摘要翻译： 集成电路包括第一电路部件，第二电路部件和用于与电路接触的外部端子。 第一电路部件经由第二部件与外部端子连接。 桥接电路将第一电路组件连接到外部端子，并且可以通过测试模式信号来激活。 在激活状态下，桥接电路将外部端子连接到第一电路部件，同时桥接第二电路部件，同时不导通处于去激活状态。 集成在半导体芯片中的电路元件可以通过可激活开关非破坏性地电测量。 位于外部端子和待测量器件之间的电路元件可以通过桥接电路从测量中排除。 该方法还使得可以并行或串行地测量多个集成器件。

公开(公告)号：US20050037564A1

公开(公告)日：2005-02-17

申请号：US10864321

申请日：2004-06-10

申请人： Michael Sommer

发明人： Michael Sommer

IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

CPC分类号： H01L27/10894 ,  H01L27/0207 ,  H01L27/10897

摘要： Method for fabricating a semiconductor memory device having auxiliary transistor structures which are required for lithography and etching processes. A protective structure for reducing leakage currents between gate conductor and doped zone is provided. The protective structure is formed as a region doped oppositely to the doped zone.

摘要翻译： 用于制造具有用于光刻和蚀刻工艺所需的辅助晶体管结构的半导体存储器件的方法。 提供了一种用于减小栅极导体和掺杂区之间漏电流的保护结构。 保护结构形成为与掺杂区相反掺杂的区域。

公开(公告)号：US06850448B2

公开(公告)日：2005-02-01

申请号：US10386148

申请日：2003-03-11

申请人： Joachim Schnabel ,  Michael Sommer

发明人： Joachim Schnabel ,  Michael Sommer

IPC分类号： G11C11/406 ,  H03K3/0231 ,  G11C7/04

CPC分类号： G11C7/04 ,  G11C11/406 ,  H03K3/0231

摘要： A circuit for generating a refresh signal for a memory cell, includes a temperature-independent current source, a temperature-independent voltage source, and a temperature-dependent reference voltage source. A capacitor's first and second terminals are connected respectively to the temperature-independent current source, and the temperature-independent voltage source. The capacitor's first terminal is connected to a first input terminal of a comparator. The comparator's second input is connected to the temperature-dependent reference voltage source. The comparator is configured to output a refresh signal in response to a difference between voltages present at the first and second inputs thereof.

摘要翻译： 用于产生用于存储单元的刷新信号的电路包括温度独立电流源，独立于温度的电压源和与温度相关的参考电压源。 电容器的第一和第二端子分别连接到与温度无关的电流源和与温度无关的电压源。 电容器的第一端子连接到比较器的第一输入端子。 比较器的第二个输入端连接到与温度相关的参考电压源。 比较器被配置为响应于存在于其第一和第二输入端的电压之间的差而输出刷新信号。