公开(公告)号：US06921624B2

公开(公告)日：2005-07-26

申请号：US10237014

申请日：2002-09-09

申请人： Akiko Hirao ,  Kazuki Matsumoto ,  Takayuki Tsukamoto ,  Hideyuki Nishizawa

发明人： Akiko Hirao ,  Kazuki Matsumoto ,  Takayuki Tsukamoto ,  Hideyuki Nishizawa

IPC分类号： G03C1/73 ,  C08K5/315 ,  C08L101/00 ,  G03G7/00 ,  G03H1/02 ,  G11B7/00 ,  G11B7/0037 ,  G11B7/0045 ,  G11B7/005 ,  G11B7/0065 ,  G11B7/135 ,  G11B7/24 ,  G11B7/244 ,  G11B7/247

CPC分类号： G11B7/247 ,  G03G7/0033 ,  G03H2260/54 ,  G11B7/0065 ,  G11B7/24044 ,  G11B7/244 ,  G11B7/2467 ,  G11B7/2531

摘要： Disclosed is an optical recording medium comprising a recording layer. The recording layer contains: a charge generation material generating an electron and a hole by light irradiation; a charge transport material transporting one of the electron and the hole; a charge trap which traps the transported one of the electron and the hole to separate the electron and the hole; and a non-linear optical material which changes optical properties of the recording layer in accordance with electric field formed by the electron and the hole being separated from each other. The non-linear optical material has an asymmetrical carbon atom and a cyclic group. Or, it is a cyclic-group-containing constituent having: an inversion symmetric pi-electron system; at least one of an electron donating group and an electron accepting group which are bonded to the inversion symmetric π-electron system; and an asymmetrical carbon atom.

摘要翻译： 公开了一种包括记录层的光学记录介质。 记录层包含：通过光照射产生电子和空穴的电荷产生材料; 输送电子和孔之一的电荷输送材料; 电荷陷阱，其捕获所输送的电子和空穴中的一个以分离电子和孔; 以及根据由电子形成的电场和彼此分离的孔改变记录层的光学特性的非线性光学材料。 非线性光学材料具有不对称碳原子和环状基团。 或者是含有环状基团的成分，具有反转对称π电子系统; 与反转对称π电子系统接合的给电子基团和电子接受基团中的至少一个; 和不对称碳原子。

公开(公告)号：US20050106353A1

公开(公告)日：2005-05-19

申请号：US10976367

申请日：2004-10-29

申请人： Tsukasa Nakai ,  Sumio Ashida ,  Keiichiro Yusu ,  Takayuki Tsukamoto ,  Noritake Oomachi ,  Naomasa Nakamura ,  Katsutaro Ichihara ,  Urara Ichihara

发明人： Tsukasa Nakai ,  Sumio Ashida ,  Keiichiro Yusu ,  Takayuki Tsukamoto ,  Noritake Oomachi ,  Naomasa Nakamura ,  Katsutaro Ichihara ,  Urara Ichihara

IPC分类号： G11B7/254 ,  B32B3/02 ,  G11B7/24 ,  G11B7/243 ,  G11B7/257

CPC分类号： G11B7/2433 ,  G11B7/252 ,  G11B7/2534 ,  G11B7/259 ,  G11B2007/24308 ,  G11B2007/24312 ,  G11B2007/24314 ,  G11B2007/24316 ,  G11B2007/25706 ,  G11B2007/2571 ,  G11B2007/25711 ,  G11B2007/25713 ,  G11B2007/25715 ,  Y10T428/21

摘要： A phase-change optical recording medium has a first information layer including a phase-change optical recording film arranged in a position close to the light incident side, a second information layer including another phase-change optical-recording film arranged in a position remote from the light incident side and an interlayer separating film arranged between the first information layer and the second information layer, in which at least one of the first information layer and the second information layer includes a noise reduction film in contact with the interlayer separating film. The noise reduction film is formed of SiOx (1≦x≦2) or SiOC.

摘要翻译： 相变光记录介质具有包括布置在靠近光入射侧的相变光记录膜的第一信息层，第二信息层，包括布置在远离光入射侧的位置的另一相变光记录膜 光入射侧和布置在第一信息层和第二信息层之间的层间隔离膜，其中第一信息层和第二信息层中的至少一个包括与层间隔离膜接触的降噪膜。 降噪膜由SiOx（1 <= x <= 2）或SiOC形成。

公开(公告)号：US06577591B2

公开(公告)日：2003-06-10

申请号：US09805128

申请日：2001-03-14

申请人： Akiko Hirao ,  Hideyuki Nishizawa ,  Kazuki Matsumoto ,  Takayuki Tsukamoto

发明人： Akiko Hirao ,  Hideyuki Nishizawa ,  Kazuki Matsumoto ,  Takayuki Tsukamoto

IPC分类号： G11B584

CPC分类号： G11B7/245 ,  B82Y10/00 ,  G11B7/00455 ,  G11B7/0052 ,  G11B7/0065 ,  G11B7/24 ,  G11B7/243 ,  G11B7/244 ,  G11B13/00 ,  G11B2007/0009 ,  G11C13/0014 ,  G11C13/0016

摘要： Disclosed is an optical recording medium having a charge generating ability capable of generating electric charges with different polarities upon irradiation with light and a charge transporting ability capable of transporting at least one of the electric charges to separate specially the electric charges from each other forming an electric field upon irradiation with light, the optical characteristics of the optical recording medium being changed depending on the electric field, wherein the charge transporting capability is imparted by a charge transporting material formed of a molecule having a charge transporting capability or a polymer containing a monomer unit having a charge transporting capability. A light intensity pattern is recorded in the optical recording medium depending on the change in the optical characteristics caused by the electric field. The average intermolecular distance of a noticed charge transporting material is defined to fall within a predetermined range.

摘要翻译： 公开了一种具有能够在照射光时产生具有不同极性的电荷的电荷产生能力的光学记录介质，以及能够传输至少一个电荷的电荷输送能力，以特别分离彼此的电荷形成电 在光照射下，光记录介质的光学特性根据电场而改变，其中电荷输送能力由具有电荷输送能力的分子形成的电荷输送材料或含有单体单元的聚合物 具有电荷输送能力。 根据由电场引起的光学特性的变化，将光强度图案记录在光学记录介质中。 注意电荷输送材料的平均分子间距离被定义为落在预定范围内。

公开(公告)号：US06353309B1

公开(公告)日：2002-03-05

申请号：US09608023

申请日：2000-06-29

申请人： Mitsuaki Ootani ,  Yoshiyuki Wasada ,  Nobuyuki Yamazaki ,  Yasushi Inoue ,  Takeshi Nakayama ,  Junichi Shimamura ,  Yuji Ebinuma ,  Takayuki Tsukamoto

发明人： Mitsuaki Ootani ,  Yoshiyuki Wasada ,  Nobuyuki Yamazaki ,  Yasushi Inoue ,  Takeshi Nakayama ,  Junichi Shimamura ,  Yuji Ebinuma ,  Takayuki Tsukamoto

IPC分类号： G05F140

CPC分类号： G05F1/575 ,  H03K17/122

摘要： The present invention provides a switching circuit and an electronic switching component having a switching semiconductor device to perform switching between a conducting state and a non-conducting state of a conducting path to thereby reduce the power loss thereof and a control method thereof. In the present invention, at least two FETs 11 and 12, wherein the FET 11 has a faster switching time and the FET 12 has a lower ON resistance. Active terminals (drains and sources) of the FETs 11 and 12 are connected to each other in parallel. By employing these FETs 11 and 12, the conversion between an ON-state and an OFF-state of the conducting path is performed. In converting from the non-conducting state to the conducting state, the control circuit 13 first turns on the FET 11 and then turns on the FET 12 when if a voltage between terminals of the FET 11 reaches around a saturation value thereof. In converting from the conducting state to the non-conducting state, the control circuit 13 first turns off the FET 12 and then turns off the FET 11 when if a voltage between terminals of the FET 11 reaches around a saturation value thereof.

摘要翻译： 本发明提供一种开关电路和具有开关半导体器件的电子开关元件，以进行导通路径的导通状态和非导通状态之间的切换，从而降低其功率损耗及其控制方法。 在本发明中，至少两个FET 11和12，其中FET 11具有更快的开关时间，并且FET 12具有较低的导通电阻。 FET 11和12的有源端子（漏极和源极）并联连接。 通过采用这些FET11,12，进行导通路径的导通状态和截止状态之间的转换。 在从非导通状态转换为导通状态时，如果FET 11的端子之间的电压达到其饱和值，则控制电路13首先接通FET 11，然后导通FET 12。 在从导通状态转换为非导通状态时，如果FET 11的端子之间的电压达到其饱和值，则控制电路13首先关断FET 12，然后关断FET 11。

公开(公告)号：US08698228B2

公开(公告)日：2014-04-15

申请号：US12886202

申请日：2010-09-20

申请人： Takeshi Araki ,  Takeshi Yamaguchi ,  Mariko Hayashi ,  Kohichi Kubo ,  Takayuki Tsukamoto

发明人： Takeshi Araki ,  Takeshi Yamaguchi ,  Mariko Hayashi ,  Kohichi Kubo ,  Takayuki Tsukamoto

IPC分类号： H01L29/792

CPC分类号： H01L27/101 ,  B82Y10/00 ,  G11B5/743 ,  G11B9/04 ,  G11B9/1472 ,  G11B9/149 ,  G11C11/22 ,  G11C13/0007 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1625 ,  H01L45/1675

摘要： According to one embodiment, a non-volatile memory device includes a stacked structure and a voltage application portion. The stacked structure includes a memory portion, and an electrode stacked with the memory portion and having a surface having a portion facing the memory portion. The voltage application portion applies a voltage to the memory portion to cause a change in a resistance in the memory portion to store information. The surface includes a first region and a second region. The first region contains at least one of a metallic element, Si, Ga, and As. The first region is conductive. The second region contains at least one of the metallic element, Si, Ga, and As, and has a content ratio of nonmetallic element higher than a content ratio of nonmetallic element in the first region. At least one of the first region and the second region has an anisotropic shape on the surface.

摘要翻译： 根据一个实施例，非易失性存储器件包括堆叠结构和电压施加部分。 堆叠结构包括存储部分和与存储器部分堆叠并具有面向存储部分的部分的表面的电极。 电压施加部分向存储器部分施加电压以引起存储器部分中的电阻的变化以存储信息。 表面包括第一区域和第二区域。 第一区域包含金属元素Si，Ga和As中的至少一种。 第一个区域是导电的。 第二区域包含金属元素Si，Ga和As中的至少一种，并且具有高于第一区域中的非金属元素的含量比的非金属元素的含量比。 第一区域和第二区域中的至少一个在表面上具有各向异性的形状。

公开(公告)号：US20120012807A1

公开(公告)日：2012-01-19

申请号：US13182095

申请日：2011-07-13

申请人： Takeshi YAMAGUCHI ,  Hirofumi Inoue ,  Reika Ichihara ,  Takayuki Tsukamoto ,  Takashi Shigeoka ,  Katsuyuki Sekine ,  Shinya Aoki

发明人： Takeshi YAMAGUCHI ,  Hirofumi Inoue ,  Reika Ichihara ,  Takayuki Tsukamoto ,  Takashi Shigeoka ,  Katsuyuki Sekine ,  Shinya Aoki

IPC分类号： H01L45/00

CPC分类号： H01L45/146 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/1233

摘要： A semiconductor memory device in an embodiment comprises memory cells, each of the memory cells disposed between a first line and a second line and having a variable resistance element and a switching element connected in series. The variable resistance element includes a variable resistance layer configured to change in resistance value thereof between a low-resistance state and a high-resistance state. The variable resistance layer is configured by a transition metal oxide. A ratio of transition metal and oxygen configuring the transition metal oxide varies between 1:1 and 1:2 along a first direction directed from the first line to the second line.

摘要翻译： 实施例中的半导体存储器件包括存储单元，每个存储单元设置在第一线和第二线之间，并且具有串联连接的可变电阻元件和开关元件。 可变电阻元件包括可变电阻层，其被配置为在低电阻状态和高电阻状态之间改变其电阻值。 可变电阻层由过渡金属氧化物构成。 构成过渡金属氧化物的过渡金属和氧的比例沿着从第一线指向第二线的第一方向在1:1和1:2之间变化。

公开(公告)号：US20110235401A1

公开(公告)日：2011-09-29

申请号：US13052214

申请日：2011-03-21

申请人： Tetsuji KUNITAKE ,  Takashi Shigeoka ,  Takayuki Tsukamoto ,  Hironori Wakai ,  Hisashi Kato

发明人： Tetsuji KUNITAKE ,  Takashi Shigeoka ,  Takayuki Tsukamoto ,  Hironori Wakai ,  Hisashi Kato

IPC分类号： G11C11/00 ,  H05K13/00

CPC分类号： H01L27/24 ,  G11C8/08 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0083 ,  H01L27/1021

摘要： A nonvolatile semiconductor memory device according to an embodiment herein includes a memory cell array. The memory cell array includes memory cells each provided between a first line and a second line and each including a variable resistor. A control circuit applies through the first and second lines a voltage necessary for a forming operation of the memory cell. A current limiting circuit limits a value of a current flowing across the memory cell during the forming operation to a certain limit value. The control circuit repeats an operation of applying the voltage by setting the limit value to a certain value and an operation of changing the limit value from the certain value, until forming of the memory cell is achieved.

摘要翻译： 根据本文实施例的非易失性半导体存储器件包括存储单元阵列。 存储单元阵列包括各自设置在第一线路和第二线路之间并且各自包括可变电阻器的存储器单元。 控制电路通过第一和第二行施加存储单元的形成操作所需的电压。 电流限制电路将在成形操作期间流过存储器单元的电流的值限制到某一极限值。 控制电路重复通过将极限值设定为一定值来施加电压的操作和从该特定值改变极限值的操作，直到实现存储单元的形成。

公开(公告)号：US20110216574A1

公开(公告)日：2011-09-08

申请号：US12886931

申请日：2010-09-21

申请人： Reika ICHIHARA ,  Takayuki Tsukamoto

发明人： Reika ICHIHARA ,  Takayuki Tsukamoto

IPC分类号： G11C11/00

CPC分类号： G11C11/00 ,  G11C2013/0083

摘要： A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the first, second lines, and each includes a variable resistor. The control circuit is configured to control a voltage applied to the memory cells. The control circuit applies a first pulse voltage to the variable resistor during a forming operation. In addition, the control circuit applies a second pulse voltage to the variable resistor during a setting operation, the second pulse voltage having a polarity opposite to the first pulse voltage. Furthermore, the control circuit applies a third pulse voltage to the variable resistor during a resetting operation, the third pulse voltage having a polarity identical to the first pulse voltage.

摘要翻译： 根据实施例的非易失性半导体存储器件包括多个第一，第二线，多个存储单元和控制电路。 多个第二线延伸以与第一线相交。 多个存储单元设置在第一和第二线的交点处，并且每个都包括可变电阻器。 控制电路被配置为控制施加到存储器单元的电压。 控制电路在成形操作期间向可变电阻器施加第一脉冲电压。 此外，控制电路在设定操作期间向可变电阻施加第二脉冲电压，第二脉冲电压具有与第一脉冲电压相反的极性。 此外，控制电路在复位操作期间向可变电阻器施加第三脉冲电压，第三脉冲电压具有与第一脉冲电压相同的极性。

公开(公告)号：US20110073927A1

公开(公告)日：2011-03-31

申请号：US12886079

申请日：2010-09-20

申请人： Takeshi ARAKI ,  Takeshi Yamaguchi ,  Mariko Hayashi ,  Kohichi Kubo ,  Takayuki Tsukamoto

发明人： Takeshi ARAKI ,  Takeshi Yamaguchi ,  Mariko Hayashi ,  Kohichi Kubo ,  Takayuki Tsukamoto

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： G11B9/1472 ,  B82Y10/00 ,  G11B5/746 ,  G11B9/04 ,  G11B9/149 ,  G11C13/0007 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/101 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1625 ,  H01L45/1675

摘要： According to one embodiment, a non-volatile memory device includes a stacked structure including a memory portion and an electrode having a surface facing the memory portion; and a voltage application portion to apply a voltage to the memory portion to change resistance. The surface includes first and second regions. The first region contains a first nonmetallic element and at least one element of a metallic element, Si, Ga, and As. The second region contains a second nonmetallic element and the at least one element. The second region has a content ratio of the second nonmetallic element higher than that in the first region. A difference in electronegativity between the second nonmetallic element and the at least one element is greater than that between the first nonmetallic element and the at least one element. At least one of the first and second regions has an anisotropic shape.

摘要翻译： 根据一个实施例，非易失性存储器件包括堆叠结构，其包括存储器部分和具有面向存储器部分的表面的电极; 以及电压施加部分，用于向存储器部分施加电压以改变电阻。 表面包括第一和第二区域。 第一区域包含第一非金属元素和金属元素Si，Ga和As的至少一种元素。 第二区域包含第二非金属元素和至少一个元素。 第二区域的第二非金属元素的含量比率高于第一区域。 第二非金属元素与至少一种元素之间的电负性的差异大于第一非金属元素与至少一种元素之间的电负性。 第一和第二区域中的至少一个具有各向异性形状。

公开(公告)号：US20110031459A1

公开(公告)日：2011-02-10

申请号：US12886254

申请日：2010-09-20

申请人： Kohichi KUBO ,  Chikayoshi Kamata ,  Takayuki Tsukamoto ,  Shinya Aoki ,  Takahiro Hirai ,  Tsukasa Nakai ,  Toshiro Hiraoka

发明人： Kohichi KUBO ,  Chikayoshi Kamata ,  Takayuki Tsukamoto ,  Shinya Aoki ,  Takahiro Hirai ,  Tsukasa Nakai ,  Toshiro Hiraoka

IPC分类号： H01L45/00

CPC分类号： B82Y10/00 ,  G11B9/04 ,  G11B9/1481 ,  G11B9/149 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/51 ,  G11C2213/53 ,  G11C2213/55 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/101

摘要： According to one embodiment, an information recording and reproducing device includes a first layer, a second layer and a recording layer. The recording layer is provided between the first layer and the second layer and being capable of reversibly changing between a first state having a first resistance and a second state having a second resistance higher than the first resistance. The recording layer includes a first compound layer and a second compound layer. The first compound layer contains a first compound. The first compound includes a first cation element and a second cation element of a type different from the first cation element. The second compound layer contains a second compound. The second compound includes a transition element having a d-orbital partially filled with electron, and the second compound includes a void site capable of storing at least one of the first cation element and the second cation element.

摘要翻译： 根据一个实施例，信息记录和再现装置包括第一层，第二层和记录层。 记录层设置在第一层和第二层之间，并且能够在具有第一电阻的第一状态和具有高于第一电阻的第二电阻的第二状态之间可逆地改变。 记录层包括第一化合物层和第二化合物层。 第一化合物层含有第一化合物。 第一化合物包括第一阳离子元件和不同于第一阳离子元件的第二阳离子元件。 第二化合物层含有第二化合物。 第二化合物包括具有部分填充有电子的d轨道的过渡元素，并且第二化合物包括能够存储第一阳离子元件和第二阳离子元素中的至少一种的空隙位置。