公开(公告)号：US11495596B2

公开(公告)日：2022-11-08

申请号：US16147512

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Uygar E. Avci ,  Daniel H. Morris ,  Ian A. Young

IPC: H01L27/06 ,  H01L27/07 ,  H01L25/18 ,  H01L29/51 ,  H01L27/02 ,  H01L29/88 ,  H01L27/11519

Abstract: An integrated circuit structure comprises a substrate having a memory region of and an adjacent logic region. A first N type well (Nwell) is formed in the substrate for the memory region and a second Nwell formed in the substrate for the logic region. A plurality of memory transistors in the memory region and a plurality of logic transistors are in the logic region, wherein ones the memory transistors include a floating gate over a channel, and a source and a drain on opposite sides of the channel. A diode portion is formed over one of the source and the drain of at least one of the memory transistors to conduct charge to the floating-gate of the at least one of the memory transistors for state retention during power gating.

公开(公告)号：US11462540B2

公开(公告)日：2022-10-04

申请号：US17142176

申请日：2021-01-05

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US11056593B2

公开(公告)日：2021-07-06

申请号：US16631059

申请日：2017-09-12

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Uygar E. Avci ,  Christopher J. Wiegand ,  Anurag Chaudhry ,  Jasmeet S. Chawla ,  Ian A Young

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/18 ,  H01L21/3105 ,  H01L21/8252

Abstract: Techniques are disclosed for forming semiconductor integrated circuits including one or more of source and drain contacts and gate electrodes comprising crystalline alloys including a transition metal. The crystalline alloys help to reduce contact resistance to the semiconductor devices. In some embodiments of the present disclosure, this reduction in contact resistance is accomplished by aligning the work function of the crystalline alloy with the work function of the source and drain regions such that a Schottky barrier height associated with an interface between the crystalline alloys and the source and drain regions is in a range of 0.3 eV or less.

公开(公告)号：US20210167073A1

公开(公告)日：2021-06-03

申请号：US16700782

申请日：2019-12-02

Applicant: Intel Corporation

Inventor： Shriram Shivaraman ,  Seung Hoon Sung ,  Ashish Verma Penumatcha ,  Uygar E. Avci

IPC: H01L27/1159 ,  G11C11/22 ,  G11C5/06 ,  H01L27/11507 ,  H01L29/78 ,  H01L29/66 ,  H01L49/02

Abstract: A device is disclosed. The device includes a substrate that includes a base portion and a fin portion that extends upward from the base portion, an insulator layer on sides and top of the fin portion, a first conductor layer on a first side surface of the insulator layer, a second conductor layer on a second side surface of the insulator layer, and a ferroelectric layer on portions of a top surface of the base portion, a portion of the insulator layer below the first conductor layer, a side and top surface of the first conductor layer, a top surface of the insulator layer above the fin portion, a side and top surface of the second conductor layer, and a portion of the insulator layer below the second conductor layer. A word line conductor is on the top surface of the ferroelectric layer.

公开(公告)号：US20210159229A1

公开(公告)日：2021-05-27

申请号：US16691163

申请日：2019-11-21

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Kinyip Phoa ,  Mauro J. Kobrinsky ,  Tahir Ghani ,  Uygar E. Avci ,  Rajesh Kumar

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L29/78 ,  H01L49/02

Abstract: Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device includes a first semiconductor nanoribbon, a second semiconductor nanoribbon, a first source or drain (S/D) region and a second S/D region in each of the first and second nanoribbons, a first gate stack at least partially surrounding a portion of the first nanoribbon between the first and second S/D regions in the first nanoribbon, and a second gate stack, not electrically coupled to the first gate stack, at least partially surrounding a portion of the second nanoribbon between the first and second S/D regions in the second nanoribbon. The device further includes a bitline coupled to the first S/D regions of both the first and second nanoribbons.

公开(公告)号：US11004868B2

公开(公告)日：2021-05-11

申请号：US16487417

申请日：2017-03-22

Applicant: Intel Corporation

Inventor： Seiyon Kim ,  Uygar E. Avci ,  Joshua M. Howard ,  Ian A. Young ,  Daniel H. Morris

IPC: H01L29/78 ,  H01L27/1159 ,  H01L21/28 ,  H01L27/11592 ,  H01L29/51

Abstract: Memory field-effect transistors and methods of manufacturing the same are disclosed. An example apparatus includes a semiconductor substrate and a ferroelectric gate insulator of a memory field-effect transistor formed within a trench having walls defined by spacers and a base defined by the semiconductor substrate. The apparatus further includes a gate conductor formed on the ferroelectric gate insulator. The ferroelectric gate insulator is to separate a bottom surface of the gate conductor and the substrate.

公开(公告)号：US10901486B2

公开(公告)日：2021-01-26

申请号：US16384715

申请日：2019-04-15

Applicant: Intel Corporation

Inventor： Kaushik Vaidyanathan ,  Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young ,  Tanay Karnik ,  Huichu Liu

IPC: G06F1/3234 ,  G06F13/40 ,  G06F1/3296 ,  G06F1/324 ,  H03K19/0185

Abstract: Described is an apparatus which comprises: a first electrical path comprising at least one driver and receiver; and a second electrical path comprising at least one driver and receiver, wherein the first and second electrical paths are to receive a same input signal, wherein the first electrical path and the second electrical path are parallel to one another and have substantially the same propagation delays, and wherein the second electrical path is enabled during a first operation mode and disabled during a second operation mode.

公开(公告)号：US20200286687A1

公开(公告)日：2020-09-10

申请号：US16296085

申请日：2019-03-07

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sou-Chi Chang ,  Nazila Haratipour ,  Seung Hoon Sung ,  Ashish Verma Penumatcha ,  Jack Kavalieros ,  Uygar E. Avci ,  Ian A. Young

IPC: H01G7/06 ,  H01L27/108 ,  H01L49/02 ,  G11C11/22

Abstract: Described is an ultra-dense ferroelectric memory. The memory is fabricated using a patterning method by that applies atomic layer deposition with selective dry and/or wet etch to increase memory density at a given via opening. A ferroelectric capacitor in one example comprises: a first structure (e.g., first electrode) comprising metal; a second structure (e.g., a second electrode) comprising metal; and a third structure comprising ferroelectric material, wherein the third structure is between and adjacent to the first and second structures, wherein a portion of the third structure is interdigitated with the first and second structures to increase surface area of the third structure. The increased surface area allows for higher memory density.

公开(公告)号：US10720504B2

公开(公告)日：2020-07-21

申请号：US15751104

申请日：2015-09-11

Applicant: Intel Corporation

Inventor： Uygar E. Avci ,  Daniel H. Morris ,  Ian A. Young

IPC: H01L29/51 ,  H01L29/78 ,  H01L27/11585 ,  H01L29/66

Abstract: Described is an apparatus which comprises a transistor including: a layer of ferroelectric material; a layer of insulating material; and an oxide layer or a metal layer sandwiched between the layer of ferroelectric material and the layer of insulating material, wherein thickness of the ferroelectric material is less than thickness of the layer of insulating material; and a driver coupled to the transistor. Described is an apparatus which comprises: a transistor including: a first oxide layer of High-K material; a second oxide layer; and a layer of nanocrystals sandwiched between the first and second oxide layers, wherein thickness of first oxide layer is greater than thickness of the second oxide layer; and a driver coupled to the transistor.

公开(公告)号：US10720434B2

公开(公告)日：2020-07-21

申请号：US16452469

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.