公开(公告)号：US20190378675A1

公开(公告)日：2019-12-12

申请号：US16391629

申请日：2019-04-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Injo Ok ,  Choonghyun Lee ,  Soon-Cheon Seo ,  Seyoung Kim

IPC: H01J21/10 ,  H01J9/18 ,  H01J19/24 ,  H01L29/788

Abstract: A method is presented for controlling an electric field from a gate structure. The method includes forming a hardmask over a fin stack including a plurality of layers, forming a first dielectric layer over the hardmask, forming a sacrificial layer over the first dielectric layer, etching the sacrificial layer to expose a top surface of the first dielectric layer, depositing a second dielectric layer in direct contact with exposed surfaces of the first dielectric layer and the sacrificial layer, removing a layer of the plurality of layers of the fin stack to define an air gap within the fin stack, and forming triangle-shaped epitaxial growths within the air gap defined within the fin stack.

公开(公告)号：US20190371900A1

公开(公告)日：2019-12-05

申请号：US16536951

申请日：2019-08-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Choonghyun Lee ,  Seyoung Kim ,  Injo Ok ,  Soon-Cheon Seo

IPC: H01L29/423 ,  H01L29/737 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L29/732

Abstract: A bipolar junction transistor includes a collector having a first surface on a first level and a second surface on a second level. A base is formed on the second level of the collector, and an emitter is formed on the base. A dielectric liner is formed on vertical sidewalls of the collector, the base and the emitter and over the first surface. A conductive region is formed adjacent to the base in the dielectric liner. A base contact is formed along one of the vertical sidewalls to connect to the base through the conductive region.

公开(公告)号：US20190355723A1

公开(公告)日：2019-11-21

申请号：US15980250

申请日：2018-05-15

Applicant: International Business Machines Corporation

Inventor： Xin Miao ,  Jingyun Zhang ,  Alexander Reznicek ,  Choonghyun Lee

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L29/161 ,  H01L21/8238

Abstract: A semiconductor structure is provided in which an nFET nanosheet stack of suspended silicon channel material nanosheets is present in an nFET device region and a pFET nanosheet stack of suspended silicon germanium alloy channel material nanosheets is present in a pFET device region. The silicon channel material nanosheets of the nFET nanosheet stack are off-set by one nanosheet from the silicon germanium alloy channel material nanosheets of the pFET nanosheet stack.

公开(公告)号：US10468532B1

公开(公告)日：2019-11-05

申请号：US15973043

申请日：2018-05-07

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Xin Miao ,  Jingyun Zhang ,  Choonghyun Lee

IPC: H01L29/786 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L27/092

Abstract: A thin layer of lattice matched wide bandgap semiconductor material having semi-insulating properties is employed as an isolation layer between the substrate and a vertical stack of suspended semiconductor channel material nanosheets. The presence of such an isolation layer eliminates the parasitic leakage path between the source region and the drain region that typically occurs through the substrate, while not interfering with the CMOS device that is formed around the semiconductor channel material nanosheets.

公开(公告)号：US20190334017A1

公开(公告)日：2019-10-31

申请号：US16505411

申请日：2019-07-08

Applicant: International Business Machines Corporation

Inventor： Shogo Mochizuki ,  Michael P. Belyansky ,  Choonghyun Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234

Abstract: A VFET device with a dual top spacer to prevent source/drain-to-gate short, and techniques for formation thereof are provided. In one aspect, a method of forming a VFET device includes: etching vertical fin channels in a substrate; forming a bottom source and drain in the substrate beneath the vertical fin channels; forming a bottom spacer on the bottom source and drain; depositing a gate dielectric and gate conductor onto the vertical fin channels; recessing the gate dielectric and gate conductor to expose tops of the vertical fin channels; selectively forming dielectric spacers on end portions of the gate dielectric and gate conductor adjacent to the tops of the vertical fin channels; depositing an encapsulation layer onto the vertical fin channels; recessing the encapsulation layer with the dielectric spacers serving as an etch stop; and forming top source and drains. A VFET device formed using the present techniques is also provided.

公开(公告)号：US20190326395A1

公开(公告)日：2019-10-24

申请号：US15959062

申请日：2018-04-20

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Pouya Hashemi ,  Choonghyun Lee ,  Alexander Reznicek ,  Jingyun Zhang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02

Abstract: A semiconductor device includes a substrate material with a semiconductor material with a predetermined crystal orientation, a gate stack having a plurality of nanosheet channel layers, each nanosheet channel layer being controlled by metal gate layers located above and below the nanosheet channel layer, each nanosheet channel layer having the same semiconductor material and crystal orientation as that of the substrate, and a source/drain region on opposite sides of the gate stack. Each source/drain region includes bridging structures respectively connected to each nanosheet channel layer.

公开(公告)号：US20190326354A1

公开(公告)日：2019-10-24

申请号：US15960670

申请日：2018-04-24

Applicant: International Business Machines Corporation

Inventor： Soon-Cheon Seo ,  Seyoung Kim ,  Injo Ok ,  Choonghyun Lee ,  Kisup Chung

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02

Abstract: A method of forming a bottom electrode for MRAM comprises: depositing a conductive material into a trench in a substrate and planarizing; depositing a selective cap on the conductive material; depositing a layer of high stress material on upper surfaces of the substrate and the cap; patterning the high stress material to remove the layer of high stress material on the upper surfaces of the substrate and leaving the layer of high stress material on the upper surfaces of the cap; depositing a layer of dielectric material on the upper surfaces of the substrate and on upper surfaces of the high stress material on the cap; planarizing the layer of dielectric material; and forming a magnetic tunnel junction stack on the dielectric material over the conductive material.

公开(公告)号：US10453844B2

公开(公告)日：2019-10-22

申请号：US15833543

申请日：2017-12-06

Applicant: International Business Machines Corporation

Inventor： Injo Ok ,  Choonghyun Lee ,  Soon-Cheon Seo ,  Seyoung Kim

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238

Abstract: Techniques for enhancing VFET performance are provided. In one aspect, a method of forming a VFET device includes: patterning a fin(s) in a substrate; forming bottom source and drains at a base of the fin(s); forming bottom spacers on the bottom source and drains; forming a gate along sidewalls of the fin(s); recessing the gate to expose a top portion of the fin(s); forming an oxide layer along the sidewalls of the top portion of the fin(s); depositing a charged layer over the fin(s) in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the fin(s) forming a dipole; forming top spacers above the gate; and forming top source and drains above the top spacers. A method of forming a VFET device having both NFETs and PFETs is also provided as are VFET devices formed by the present techniques.

公开(公告)号：US20190319094A1

公开(公告)日：2019-10-17

申请号：US15954663

申请日：2018-04-17

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Choonghyun Lee ,  Shogo Mochizuki

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66

Abstract: Vertical field effect transistor (VFET) structures and methods of fabrication with improved junction sharpness and reduced parasitic capacitance between the top source or drain and the surrounding metal gate includes a non-uniform top spacer in the top source or drain formed by an oxidation process. The top spacer has a thickness that is thinner at an interface between the top source or drain region and the vertically oriented channel region of the fin structure relative to the thickness of the top spacer layer away from the interface.

公开(公告)号：US20190295844A1

公开(公告)日：2019-09-26

申请号：US15933949

申请日：2018-03-23

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Ruqiang Bao ,  Gen Tsutsui ,  Dechao Guo

IPC: H01L21/02 ,  H01L27/12 ,  H01L27/092 ,  H01L21/324 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/66

Abstract: Improved gate stack designs for Si and SiGe dual channel devices are provided. In one aspect, a method for forming a dual channel device includes: forming fins on a substrate, the fins including Si fins in combination with SiGe fins as dual channels of an analog device and a logic device, with the analog device and the logic device each having a Si fin and a SiGe fin; forming a silicon germanium oxide (SiGeOx) layer on the SiGe fins; annealing the SiGeOx layer to form a Si-rich layer on the SiGe fins via a reaction between SiGeOx and SiGe; and forming metal gates over the Si fins and over the Si-rich layer on the SiGe fins. A dual channel device is also provided.