公开(公告)号：US11168400B2

公开(公告)日：2021-11-09

申请号：US16014579

申请日：2018-06-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles L. Arvin ,  Brian Michael Erwin ,  Chris Muzzy ,  Thomas Weiss

IPC: C25D5/02 ,  C23C18/16 ,  H05K3/18 ,  C23C18/18

Abstract: At least one plating pen is brought into aligned relationship with at least one hole defined in a board. The pen includes a central retractable protrusion, a first shell surrounding the protrusion and defining a first annular channel therewith, and a second shell surrounding the first shell and defining a second annular channel therewith. The protrusion is lowered to block the hole and plating material is flowed down the first channel to a surface of the board and up into the second channel, to form an initial deposit on the board surface. The protrusion is raised to unblock the hole, and plating material is flowed down the first annular channel to side walls of the hole and up into the second annular channel, to deposit the material on the side walls of the hole.

公开(公告)号：US11031373B2

公开(公告)日：2021-06-08

申请号：US16369532

申请日：2019-03-29

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Bhupender Singh ,  Richard Francis Indyk ,  Steve Ostrander ,  Thomas Weiss ,  Mark Kapfhammer

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

Abstract: A multi-die integrated circuit device and a method of fabricating the multi-die integrated circuit device involve a substrate. Two or more dice include components that implement functionality of the multi-die integrated circuit. The components include logic gates. The multi-die integrated circuit device also includes a spacer disposed between the substrate and each of the two or more dice. Each of the two or more dice makes direct electrical contact with the substrate without making direct electrical contact with the spacer through holes in the spacer.

公开(公告)号：US10957650B2

公开(公告)日：2021-03-23

申请号：US16546912

申请日：2019-08-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles L. Arvin ,  Karen P. McLaughlin ,  Brian W. Quinlan ,  Thomas Weiss

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: A module including a first semiconductor device, a second semiconductor device, a bridge support structure and a base substrate. The semiconductor devices each having first bonding pads having a first solder joined with the base substrate and the semiconductor devices each having second and third bonding pads joined to second and third bonding pads on the bridge support structure by a second solder and a third solder, respectively, on the second and third bonding pads; the semiconductor devices positioned adjacent to each other such that the bridge support structure joins to both of the semiconductor devices by the second and third solders wherein the third bonding pads are larger than the second bonding pads and the third bonding pads are at a larger pitch than the second bonding pads.

公开(公告)号：US10892249B2

公开(公告)日：2021-01-12

申请号：US16427631

申请日：2019-05-31

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Mark W. Kapfhammer ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Thomas Weiss

IPC: H01L23/52 ,  H01L21/56 ,  H01L23/40 ,  H01L23/34 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/538 ,  H01L23/00

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

公开(公告)号：US20200013732A1

公开(公告)日：2020-01-09

申请号：US16575549

申请日：2019-09-19

Applicant: International Business Machines Corporation

Inventor： Kamal K. Sikka ,  Krishna R. Tunga ,  Hilton T. Toy ,  Thomas Weiss ,  Shidong Li ,  Sushumna Iruvanti

IPC: H01L23/00 ,  H05K3/30 ,  H01L23/498 ,  H01L21/48 ,  H01L21/027

Abstract: A technique relates to an electronic package. A substrate is configured to receive a chip. A stiffener is attached to the substrate. The stiffener includes a core material with a first material formed on opposing sides of the core material.

公开(公告)号：US20190312011A1

公开(公告)日：2019-10-10

申请号：US16427631

申请日：2019-05-31

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Mark W. Kapfhammer ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Thomas Weiss

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L23/13

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

公开(公告)号：US10178818B2

公开(公告)日：2019-01-08

申请号：US15835585

申请日：2017-12-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael J. Fisher ,  David C. Long ,  Michael T. Peets ,  Thomas Weiss

IPC: H05K13/00 ,  H05K5/02 ,  H05K3/10

Abstract: Methods of fabricating tamper-respondent assemblies are provided which include an electronic enclosure, a tamper-respondent electronic circuit structure, and at least one security element. The electronic enclosure encloses, at least in part, at least one electronic component to be protected, and includes an inner surface. The tamper-respondent electronic circuit structure includes a tamper-respondent sensor covering, at least in part, the inner surface of the electronic enclosure, and the at least one security element overlies and physically secures in place, at least in part, the tamper-respondent sensor covering, at least in part, the inner surface of the electronic enclosure. In enhanced embodiments, the electronic enclosure is secured to a multilayer circuit board which includes an embedded tamper-respondent sensor, and together, the tamper-respondent sensor covering the inner surface of the electronic enclosure and the embedded tamper-respondent sensor within the multilayer circuit board define a secure volume about the electronic component(s).

公开(公告)号：US10177075B2

公开(公告)日：2019-01-08

申请号：US15186588

申请日：2016-06-20

Applicant: International Business Machines Corporation

Inventor： Raschid J. Bezama ,  David C. Long ,  Govindarajan Natarajan ,  Thomas Weiss

IPC: F28F7/00 ,  H01L23/473 ,  F28D15/00 ,  H01L23/373 ,  F28F13/00

Abstract: A heat sink and method for using the same for use in cooling an integrated circuit (IC) chip is provided herein. The heat sink includes a manifold block, a liquid-filled cooling system, and a compliant foil affixed to the manifold block and backed by a liquid in the closed loop cooling system. The pressure provided by the liquid behind the foil causes the foil to bow, and to conform to non-planarities in the surface of the IC chip, thus reducing air gaps and increasing thermal coupling between the IC chip and the heat sink.

公开(公告)号：US09913362B2

公开(公告)日：2018-03-06

申请号：US14941860

申请日：2015-11-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： William L. Brodsky ,  James A. Busby ,  Zachary T. Dreiss ,  Michael J. Fisher ,  David C. Long ,  William Santiago-Fernandez ,  Thomas Weiss

IPC: B32B41/00 ,  H05K1/02 ,  H05K1/18 ,  G06F21/87 ,  H05K5/02

CPC classification number: H05K1/0213 ,  G06F21/87 ,  H05K1/0275 ,  H05K1/183 ,  H05K5/0208 ,  H05K2201/10151

Abstract: Methods of fabricating tamper-respondent assemblies with bond protection are provided which include at least one tamper-respondent sensor having unexposed circuit lines forming, at least in part, one or more tamper-detect network(s), and the tamper-respondent sensor having at least one external bond region. The tamper-respondent assembly further includes at least one conductive trace and an adhesive. The conductive trace(s) forms, at least in part, the one or more tamper-detect network(s), and is exposed, at least in part, on the tamper-respondent sensor(s) within the external bond region(s). The adhesive contacts the conductive trace(s) within the external bond region(s) of the tamper-respondent sensor(s), and the adhesive, in part, facilitates securing the at least one tamper-respondent sensor within the tamper-respondent assembly. In enhanced embodiments, the conductive trace(s) is a chemically compromisable conductor susceptible to damage during a chemical attack on the adhesive within the external bond region(s).

公开(公告)号：US09673177B1

公开(公告)日：2017-06-06

申请号：US14969905

申请日：2015-12-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin V. Fasano ,  Mark W. Kapfhammer ,  David J. Lewison ,  Thomas E. Lombardi ,  Thomas Weiss

IPC: H01L23/31 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/06513

Abstract: A technique relates to forming a chip assembly. Top and bottom chip stack elements containing solder pads and a solder material are provided. Soluble standoffs are applied to the bottom chip stack element. The chip stack elements are aligned to bring the top solder pad in proximity to the bottom solder pad and the temperature is raised to a temperature above the melting temperature of the solder material to form a connected chip assembly. The connected chip assembly is cooled to re-solidify the solder material and soluble standoffs are removed from the connected chip assembly.