公开(公告)号：US5977763A

公开(公告)日：1999-11-02

申请号：US607688

申请日：1996-02-27

申请人： Daniel R. Loughmiller ,  Joseph C. Sher ,  Kevin G. Duesman

发明人： Daniel R. Loughmiller ,  Joseph C. Sher ,  Kevin G. Duesman

IPC分类号： G01R31/28 ,  G01R31/02

CPC分类号： G01R31/2884

摘要： A circuit (10) for reading a voltage at a voltage source (14) of an integrated circuit (12). In one version, the circuit (110) involves a pass circuit (118) that has an input coupled to the node (114) of the integrated circuit (12). The circuit (110) provides a measurement of the voltage at the node (114) as an output to a pin (116). A reset circuit (122) is coupled to the pass circuit (118) and is operable to activate and reset the pass circuit (118). Finally, a pass control circuit (120) is coupled to provide an output signal to the pass circuit (118) that drives the pass circuit (118) when active to pass the voltage at the node (114) to the pin (116).

摘要翻译： 一种用于读取集成电路（12）的电压源（14）处的电压的电路（10）。 在一个版本中，电路（110）涉及通过电路（118），其具有耦合到集成电路（12）的节点（114）的输入。 电路（110）提供节点（114）处的电压的测量作为针（116）的输出。 复位电路（122）耦合到通过电路（118）并且可操作以激活和复位通过电路（118）。 最后，当激活以将节点（114）处的电压传递到引脚（116）时，通过控制电路（120）被耦合以向传递电路（118）提供驱动通过电路（118）的输出信号。

公开(公告)号：US5834820A

公开(公告)日：1998-11-10

申请号：US543160

申请日：1995-10-13

申请人： Stephen L. Casper ,  Brian M. Shirley ,  Kevin G. Duesman

发明人： Stephen L. Casper ,  Brian M. Shirley ,  Kevin G. Duesman

IPC分类号： H01L21/765 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L21/765 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/10805 ,  H01L21/823481 ,  Y10T307/839

摘要： The provision of an isolation gate connecting unassociated active areas of adjacent transistors formed in a semiconductor substrate provides effective isolation of the adjacent transistors with no additional process steps required. The isolation gate is tied to a reference to ensure that a channel between the unassociated active areas is not formed, and effective isolation is provided. The adjacent transistors are cross coupled to form sense amplifiers for dynamic random access memory devices.

摘要翻译： 连接在半导体衬底中形成的相邻晶体管的非相关有源区的隔离栅的提供不需要额外的工艺步骤来提供相邻晶体管的有效隔离。 隔离栅极连接到参考，以确保未形成非相关活动区域之间的通道，并提供有效的隔离。 相邻的晶体管被​​交叉耦合以形成用于动态随机存取存储器件的读出放大器。

公开(公告)号：US5796666A

公开(公告)日：1998-08-18

申请号：US831609

申请日：1997-04-10

申请人： Brian M. Shirley ,  Kevin G. Duesman

发明人： Brian M. Shirley ,  Kevin G. Duesman

IPC分类号： G11C7/10 ,  G11C7/00 ,  G11C7/02

CPC分类号： G11C7/1048

摘要： A helper flip-flop device is coupled to a pair of I/O DIGIT lines in a DC bias current sensing based dynamic random access memory (DRAM) device for ensuring that one of the DIGIT lines returns to as low a voltage as possible following a memory access. A sense amplifier is coupled to the I/O lines to amplify the differential voltage appearing on the lines following access of a memory cell. The helper flip-flop, when activated at the same time the DC bias is removed, sinks current from the low line to ground, effectively reducing its voltage to near ground to allow faster release of the row access signal.

公开(公告)号：US5787044A

公开(公告)日：1998-07-28

申请号：US835867

申请日：1997-04-08

申请人： Kevin G. Duesman

发明人： Kevin G. Duesman

IPC分类号： G11C11/4074 ,  G11C29/00 ,  G11C1/40

CPC分类号： G11C29/832 ,  G11C11/4074 ,  G11C29/70

摘要： An array of memory cells are arranged in rows and columns. The array includes a plurality of cell plates that are each coupled to at least one of the memory cells. A generator produces a bias voltage. A plurality of isolation circuits are each coupled between the generator and one or more of the cell plates. Each isolation circuit provides the bias voltage to the cell plate or plates to which the isolation circuit is coupled. The cell plates may be coupled to memory cells from a plurality of the columns. Additionally, each of the isolation circuits may selectively provide, in response to a control signal, the bias voltage to the cell plate or plates to which the isolation circuit is coupled.

公开(公告)号：USRE35764E

公开(公告)日：1998-04-07

申请号：US713757

申请日：1996-09-13

申请人： Stephen L. Casper ,  Kevin G. Duesman

发明人： Stephen L. Casper ,  Kevin G. Duesman

IPC分类号： H03K17/16 ,  H03K17/08 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0948 ,  H03K19/20

CPC分类号： H03K19/00361 ,  H03K19/00315

摘要： A new inverting output driver circuit is disclosed that reduces electron injection into the substrate by the drain of the circuit's pull-up field effect transistor. This is accomplished by adding additional circuitry that allows the gate voltage of the pull-up transistor to track the source voltage. The output circuit makes use of an inverter having an output node (hereinafter the intermediate node) coupled to V.sub.CC through a first P-channel FET, and to ground through first and second series coupled N-channel FETs, respectively. The gates of the P-channel FET and the first N-channel FET are coupled to and controlled by an input node. The inverter output node controls the gate of third N-channel FET, through which a final output node is coupled to V.sub.CC. The intermediate node is coupled to the final output node through a fourth N-channel FET, the gate of which is held at ground potential. The gate of the second N-channel FET is coupled to V.sub.CC through a second P-channel FET and to the final output node through a fifth N-channel FET which has much greater drive than the second P-channel FET; the gates of both the second P-channel FET and the fifth N-channel FET also being held at ground potential. Certain obvious variations of the circuit are possible. For example, the function of the first and second N-channel FETs may be reversed. In addition, the second P-channel FET functions as a resistor, and may be replaced with any device which functions as a resistor.

摘要翻译： 公开了一种新的反相输出驱动器电路，其通过电路的上拉场效应晶体管的漏极减少到衬底中的电子注入。 这是通过添加允许上拉晶体管的栅极电压跟踪源极电压的附加电路来实现的。 输出电路使用具有通过第一P沟道FET耦合到VCC的输出节点（以下称为中间节点）的逆变器，并且分别通过第一和第二串联耦合的N沟道FET接地。 P沟道FET和第一N沟道FET的栅极耦合到输入节点并由输入节点控制。 逆变器输出节点控制第三N沟道FET的栅极，最终的输出节点通过该栅极耦合到VCC。 中间节点通过第四N沟道FET耦合到最终输出节点，第四N沟道FET的栅极保持在地电位。 第二N沟道FET的栅极通过第二P沟道FET耦合到VCC，并通过具有比第二P沟道FET大得多的驱动的第五N沟道FET耦合到最终输出节点; 第二P沟道FET和第五N沟道FET两者的栅极也保持接地电位。 电路的某些明显变化是可能的。 例如，第一和第二N沟道FET的功能可以颠倒。 此外，第二P沟道FET用作电阻器，并且可以用用作电阻器的任何器件替代。

公开(公告)号：US5539347A

公开(公告)日：1996-07-23

申请号：US393580

申请日：1995-02-23

申请人： Kevin G. Duesman

发明人： Kevin G. Duesman

IPC分类号： H03K17/22 ,  H03K3/284

CPC分类号： H03K17/22

摘要： A circuit, responsive to the application of primary power, generates signals to establish the initial state of a logic circuit. Generated signals are interposed on the logic circuit's input signal line until initialization is complete. After initialization, the logic circuit's input signal line is recoupled for normal operation.

摘要翻译： 响应于主电源的应用的电路产生信号以建立逻辑电路的初始状态。 生成的信号插入到逻辑电路的输入信号线上，直到初始化完成。 在初始化之后，逻辑电路的输入信号线被重新连接以进行正常操作。

公开(公告)号：US20120001245A1

公开(公告)日：2012-01-05

申请号：US13231554

申请日：2011-09-13

申请人： Kurt D. Beigel ,  Jigish D. Trivedi ,  Kevin G. Duesman

发明人： Kurt D. Beigel ,  Jigish D. Trivedi ,  Kevin G. Duesman

IPC分类号： H01L27/108 ,  H01L27/105

CPC分类号： H01L29/66621 ,  H01L27/10876

摘要： Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.

摘要翻译： 公开了具有凹入式存取装置的半导体存储器件。 在一些实施例中，形成凹陷进入装置的方法包括在衬底材料中形成器件凹部，该衬底材料延伸到衬底中的第一深度，该第一深度包括凹陷中的栅极氧化物层。 装置凹部可以延伸到大于第一深度的第二深度，以形成装置凹部的延伸部分。 场氧化物层可以设置在器件凹部的内部，其内部延伸到器件凹部的内部并进入衬底。 活性区域可以形成在衬底中，其邻接场氧化物层，并且栅极材料可以沉积到器件凹部中。

公开(公告)号：US07730372B2

公开(公告)日：2010-06-01

申请号：US12233334

申请日：2008-09-18

申请人： Warren M. Farnworth ,  James M. Wark ,  Eric S. Nelson ,  Kevin G. Duesman

发明人： Warren M. Farnworth ,  James M. Wark ,  Eric S. Nelson ,  Kevin G. Duesman

IPC分类号： G01R31/28

CPC分类号： G11C29/785 ,  G01R31/2884 ,  G01R31/31701 ,  G01R31/31719 ,  G01R31/318513 ,  G11C29/1201 ,  G11C29/46 ,  G11C29/80 ,  G11C29/808 ,  H01L22/22 ,  H01L2224/48091 ,  H01L2224/48227 ,  H04J2203/0062 ,  H01L2924/00014

摘要： An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable bond pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable bond pads to one of the MCM's ground pins. By applying a supply voltage to the test mode enable bond pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a ground voltage applied to the test mode enable bond pads through the ground pins so the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging.

摘要翻译： 诸如多芯片模块（MCM）的IC模块包括多个IC芯片，每个具有测试模式使能焊盘，例如输出使能焊盘。 集成到MCM基板中的保险丝将每个管芯的测试模式使能接合焊盘连接到MCM的无连接（N / C）引脚之一，并且连接到衬底中的电阻将测试模式使能焊盘连接到MCM的一个接地 针脚。 通过向测试模式施加电源电压，使焊盘通过N / C引脚，在骰子中启动测试模式。 一旦测试完成，保险丝可能会被熔断，并且施加到测试模式的接地电压使得接合焊盘通过接地引脚，使得电阻器禁用骰子中的测试模式并启动操作模式。 因此，封装在IC模块中的裸片可以在封装后进行测试。

公开(公告)号：US07276754B2

公开(公告)日：2007-10-02

申请号：US11010951

申请日：2005-08-04

申请人： Lucien J. Bissey ,  Kevin G. Duesman

发明人： Lucien J. Bissey ,  Kevin G. Duesman

IPC分类号： H01L27/108

CPC分类号： H01L29/7827 ,  H01L21/2257 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/11803 ,  H01L29/42392

摘要： A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

摘要翻译： 具有具有环形栅极区域的垂直取向的存取晶体管的存储器结构和用于制造该结构的方法。 更具体地，制造晶体管，使得晶体管的沟道相对于衬底的表面向外延伸。 围绕垂直通道制造环形门，使得其部分地或完全地围绕通道。 还可以实现埋置的环形位线。 在用环形栅极制造垂直取向的晶体管之后，可以在晶体管上制造存储器件以提供存储器单元。

公开(公告)号：US07142446B2

公开(公告)日：2006-11-28

申请号：US10902728

申请日：2004-07-29

申请人： Scott J. Derner ,  Stephen R. Porter ,  Scot M. Graham ,  Ethan A. Williford ,  Kevin G. Duesman

发明人： Scott J. Derner ,  Stephen R. Porter ,  Scot M. Graham ,  Ethan A. Williford ,  Kevin G. Duesman

IPC分类号： G11C11/24

CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C7/1048 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4096 ,  G11C2207/002

摘要： A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline voltage. The translated signals prevent the peripheral devices from conducting current in the wordline off mode, even if a wordline-to-digitline short should occur. The control signals may include a column select signal for a column select device and an active pull-up signal for a sense amplifier, among others. Additionally, an equalization circuit having high and low resistance components is provided for the memory device. The equalization circuit limits current, even if a wordline-to-digitline short occurs.