利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

195 条记录 (耗时 0.034 秒)

    BORDERLESS CONTACT STRUCTURE
    72.
    发明申请
    BORDERLESS CONTACT STRUCTURE 有权
    无边界接触结构

    公开(公告)号：US20130181261A1

    公开(公告)日：2013-07-18

    申请号：US13348894

    申请日：2012-01-12

    申请人： VEERARAGHAVAN S. BASKER ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    发明人： VEERARAGHAVAN S. BASKER ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/20

    CPC分类号： H01L29/66545 ,  H01L21/76897 ,  H01L29/66628 ,  H01L29/78

    摘要： A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on a semiconductor material. The method further includes removing the sealing material from over the gate structure and on the semiconductor material, leaving the sealing material within the space. The method further includes forming an interlevel dielectric material over the gate structure. The method further includes patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure. The method further includes forming a contact in the opening formed in the interlevel dielectric material.

    摘要翻译： 公开了无边界接触结构或部分无边界接触结构和制造方法。 该方法包括在栅极结构内形成栅极结构和由间隔物限定的空间。 该方法还包括在该空间中，在栅极结构上和半导体材料上覆盖密封材料。 该方法还包括从栅极结构和半导体材料上方移除密封材料，将密封材料留在空间内。 该方法还包括在栅极结构上形成层间电介质材料。 该方法进一步包括图案化层间电介质材料以形成暴露半导体材料和栅极结构的一部分的开口。 该方法还包括在形成在层间电介质材料中的开口中形成接触。

    Interconnect structure for electromigration enhancement
    73.
    发明授权
    Interconnect structure for electromigration enhancement 有权
    用于电迁移增强的互连结构

    公开(公告)号：US08354751B2

    公开(公告)日：2013-01-15

    申请号：US12139704

    申请日：2008-06-16

    申请人： David V. Horak ,  Shom Ponoth ,  Chih-Chao Yang

    发明人： David V. Horak ,  Shom Ponoth ,  Chih-Chao Yang

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76849 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect structure having enhanced electromigration resistance is provided in which a lower portion of a via opening includes a multi-layered liner. The multi-layered liner includes, from a patterned surface of a dielectric material outwards, a diffusion barrier, a multi-material layer and a metal-containing hard mask. The multi-material layer includes a first material layer comprised of residue from an underlying dielectric capping layer, and a second material layer comprised of residue from an underlying metallic capping layer. The present invention also provides a method of fabricating such an interconnect structure which includes the multi-layered liner within a lower portion of a via opening formed within a dielectric material.

    摘要翻译： 提供具有增强的电迁移阻力的互连结构，其中通路孔的下部包括多层衬垫。 多层衬垫包括从电介质材料的图案化表面向外扩散阻挡层，多材料层和含金属硬掩模。 多材料层包括由下面的电介质覆盖层的残留物构成的第一材料层和由下面的金属覆盖层的残留物构成的第二材料层。 本发明还提供一种制造这种互连结构的方法，其包括在介电材料内形成的通路孔的下部内的多层衬垫。

    Forming borderless contact for transistors in a replacement metal gate process
    75.
    发明授权
    Forming borderless contact for transistors in a replacement metal gate process 有权
    在替代金属栅极工艺中形成晶体管的无边界接触

    公开(公告)号：US08349674B2

    公开(公告)日：2013-01-08

    申请号：US13073151

    申请日：2011-03-28

    申请人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

    发明人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

    IPC分类号： H01L21/338

    CPC分类号： H01L29/66545 ,  H01L21/76897 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66553

    摘要： Embodiments of the present invention provide a method of forming a semiconductor structure. The method includes creating an opening inside a dielectric layer, the dielectric layer being formed on top of a substrate and the opening exposing a channel region of a transistor in the substrate; depositing a work-function layer lining the opening and covering the channel region; forming a gate conductor covering a first portion of the work-function layer, the first portion of the work-function layer being on top of the channel region; and removing a second portion of the work-function layer, the second portion of the work-function layer surrounding the first portion of the work-function layer, wherein the removal of the second portion of the work-function layer insulates the first portion of the work-function layer from rest of the work-function layer.

    摘要翻译： 本发明的实施例提供了形成半导体结构的方法。 该方法包括在电介质层内形成开口，介电层形成在衬底的顶部，并且该开口暴露衬底中晶体管的沟道区; 沉积衬套开口并覆盖通道区域的功函数层; 形成覆盖所述功函数层的第一部分的栅极导体，所述功函数层的所述第一部分位于所述沟道区的顶部; 并且去除所述功函数层的第二部分，所述功函数层的包围所述功函数层的第一部分的所述第二部分，其中所述功函数层的所述第二部分的去除使所述功函数层的第一部分绝缘 工作功能层的工作功能层。

    FORMING BORDERLESS CONTACT FOR TRANSISTORS IN A REPLACEMENT METAL GATE PROCESS
    77.
    发明申请
    FORMING BORDERLESS CONTACT FOR TRANSISTORS IN A REPLACEMENT METAL GATE PROCESS 有权
    在替代金属门过程中形成晶体管的无边界接触

    公开(公告)号：US20120248508A1

    公开(公告)日：2012-10-04

    申请号：US13073151

    申请日：2011-03-28

    申请人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

    发明人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

    IPC分类号： H01L29/772 ,  H01L21/28

    CPC分类号： H01L29/66545 ,  H01L21/76897 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66553

    摘要： Embodiments of the present invention provide a method of forming a semiconductor structure. The method includes creating an opening inside a dielectric layer, the dielectric layer being formed on top of a substrate and the opening exposing a channel region of a transistor in the substrate; depositing a work-function layer lining the opening and covering the channel region; forming a gate conductor covering a first portion of the work-function layer, the first portion of the work-function layer being on top of the channel region; and removing a second portion of the work-function layer, the second portion of the work-function layer surrounding the first portion of the work-function layer, wherein the removal of the second portion of the work-function layer insulates the first portion of the work-function layer from rest of the work-function layer.

    摘要翻译： 本发明的实施例提供一种形成半导体结构的方法。 该方法包括在电介质层内形成开口，介电层形成在衬底的顶部，并且该开口暴露衬底中晶体管的沟道区; 沉积衬套开口并覆盖通道区域的功函数层; 形成覆盖所述功函数层的第一部分的栅极导体，所述功函数层的所述第一部分位于所述沟道区的顶部; 并且去除所述功函数层的第二部分，所述功函数层的包围所述功函数层的第一部分的所述第二部分，其中所述功函数层的所述第二部分的去除使所述功函数层的第一部分绝缘 工作功能层的工作功能层。

    SUBLITHOGRAPHIC PATTERNING EMPLOYING IMAGE TRANSFER OF A CONTROLLABLY DAMAGED DIELECTRIC SIDEWALL
    79.
    发明申请
    SUBLITHOGRAPHIC PATTERNING EMPLOYING IMAGE TRANSFER OF A CONTROLLABLY DAMAGED DIELECTRIC SIDEWALL 失效
    利用控制型电介质边界进行图像传输的分层图案

    公开(公告)号：US20120104619A1

    公开(公告)日：2012-05-03

    申请号：US12913116

    申请日：2010-10-27

    申请人： Shom Ponoth ,  David V. Horak ,  Chih-Chao Yang

    发明人： Shom Ponoth ,  David V. Horak ,  Chih-Chao Yang

    IPC分类号： H01L23/52 ,  H01L21/768

    CPC分类号： H01L23/5226 ,  H01L21/02126 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76807 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

    摘要： A first low dielectric constant (low-k) dielectric material layer is lithographically patterned to form a recessed region having expose substantially vertical sidewalls, which are subsequently damaged to de-carbonize a surface portion at the sidewalls having a sublithographic width. A second low-k dielectric material layer is deposited to fill the recessed region and planarized to exposed top surfaces of the damaged low-k dielectric material portion. The damaged low-k dielectric material portion is removed selective to the first and second low-k dielectric material layers to form a trench with a sublithographic width. A portion of the pattern of the sublithographic-width trench is transferred into a metallic layer and optionally to an underlying dielectric masking material layer to define a trench with a sublithographic width, which can be employed as a template to confine the widths of via holes and line trenches to be subsequently formed in an interconnect-level dielectric material layer.

    摘要翻译： 第一低介电常数（低k）电介质材料层被光刻图案化以形成具有暴露基本上垂直侧壁的凹陷区域，其随后被损坏以使具有亚光刻宽度的侧壁处的表面部分脱碳。 沉积第二低k电介质材料层以填充凹陷区域并平坦化到损坏的低k电介质材料部分的暴露的顶表面。 选择性地去除损坏的低k电介质材料部分到第一和第二低k电介质材料层以形成具有亚光刻宽度的沟槽。 亚光刻宽度沟槽的图案的一部分被转移到金属层中，并且可选地转移到下面的介电掩模材料层以限定具有亚光刻宽度的沟槽，其可以用作模板以限制通孔的宽度和 随后在互连级介电材料层中形成线沟槽。

    BORDERLESS INTERCONNECT LINE STRUCTURE SELF-ALIGNED TO UPPER AND LOWER LEVEL CONTACT VIAS
    80.
    发明申请
    BORDERLESS INTERCONNECT LINE STRUCTURE SELF-ALIGNED TO UPPER AND LOWER LEVEL CONTACT VIAS 有权
    无边界连接线结构自上而下

    公开(公告)号：US20120086128A1

    公开(公告)日：2012-04-12

    申请号：US12899911

    申请日：2010-10-07

    申请人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

    发明人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L23/528 ,  H01L21/76885 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

    摘要： A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.

    摘要翻译： 金属层沉积在其上暴露下面的金属通孔的顶表面的平坦表面上。 图案化金属层以形成至少一个金属块，其具有要形成的金属线的水平横截面积和要形成的至少一个上覆的金属通孔。 下面的金属通孔的每个上部凹陷在位于正上方的金属块的区域的外部。 至少一个金属块的上部被光刻地图案化以形成集成线和通孔结构，其包括具有基本上恒定的宽度的金属线和至少一个覆盖的金属通孔，其具有相同的基本上恒定的宽度并且与金属线无边界地对准 。 沉积和平坦化上层电介质材料层，使得至少一个上覆金属通孔的顶表面被暴露。