公开(公告)号：US20220293628A1

公开(公告)日：2022-09-15

申请号：US17249701

申请日：2021-03-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen Chen ,  Hang-Ting Lue

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  G11C16/30 ,  G11C16/26 ,  G11C16/14

Abstract: A memory device includes a stack and a plurality of memory strings respectively penetrating the stack along the first direction and including adjacent ones of the first memory string and the second memory string. The first memory string and the second memory string include conductive pillars (including first to third conductive pillars), channel structures, and memory structures. The first memory string and the second memory string share the second conductive pillar. The channel structures include first to fourth channel layers respectively extending along the first direction. The first channel layer and the second channel layer correspond to the first memory string and are separated from each other. The third channel layer and the fourth channel layer correspond to the second memory string and are separated from each other. The memory structures are disposed between the stack and the channel structures.

公开(公告)号：US11430527B1

公开(公告)日：2022-08-30

申请号：US17233590

申请日：2021-04-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Tzu-Hsuan Hsu

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/10 ,  G11C16/32 ,  G11C16/08 ,  G11C16/30 ,  G11C16/26

Abstract: A method for performing an operation in a memory device is provided. The method includes the following steps. An erasing operation is performed on one selected word line of the memory device to ensure that a plurality of first cells to be programed and a plurality of second cells to be erased connected to the selected word line have threshold voltages lower than a first predetermined level. A programming operation is performed on the selected word line, such that the first cells are suffered a first program bias and the second cells are suffered a second program bias which is lower than the first program bias.

公开(公告)号：US11257547B2

公开(公告)日：2022-02-22

申请号：US17105669

申请日：2020-11-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Tzu-Hsuan Hsu ,  Po-Kai Hsu ,  Teng-Hao Yeh ,  Hang-Ting Lue

IPC: G11C11/34 ,  G11C16/26 ,  G11C16/14 ,  G06N3/04 ,  G11C11/56

Abstract: Provided is an operation method for a memory device, the operation method comprising: performing an erase operation; performing a verify-read operation on a memory cell to generate a cell current, the memory cell including a first transistor and a second transistor; checking whether the cell current is lower than a first cell current threshold; when the cell current is not lower than the first cell current threshold, increasing a memory gate voltage until the cell current is lower than the first cell current threshold, wherein the memory gate voltage is applied to the first transistor; fixing the memory gate voltage and increasing a drain voltage; checking whether the cell current is lower than a second cell current threshold; and if the cell current is not lower than the second cell current threshold, increasing the drain voltage until the cell current is lower than the second cell current threshold.

公开(公告)号：US11133329B2

公开(公告)日：2021-09-28

申请号：US16989584

申请日：2020-08-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: H01L27/11 ,  H01L27/11597 ,  H01L27/11587 ,  G11C7/18 ,  G11C11/22 ,  G11C8/14 ,  H01L27/1159

Abstract: A 3D flash memory is provided to includes a gate stack structure comprising a plurality of gate layers electrically insulated from each other, a cylindrical channel pillar vertically extending through each gate layer of the gate stack structure, a first conductive pillar vertically extending through the gate stack structure, the first conductive pillar being located within the cylindrical channel pillar and being electrically connected to the cylindrical channel pillar, and a second conductive pillar extending through the gate stack structure, the second conductive pillar being located within the cylindrical channel pillar and being electrically connected to the cylindrical channel pillar, the first conductive pillar and the second conductive pillar being separated from each other. The 3D flash memory also includes a ferroelectric layer disposed between gate layers of the gate stack structure and the cylindrical channel pillar.

公开(公告)号：US11011234B1

公开(公告)日：2021-05-18

申请号：US16736029

申请日：2020-01-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Yi-Ching Liu

IPC: G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: The present disclosure relates to a non-volatile memory and operating method thereof. The non-volatile memory includes multiple memory strings, multiple bit switch units, a memory operation circuit and multiple source switch units. The bit switch units are electrically connected to the memory strings. The memory operation circuit is electrically connected to the bit switch units to transmit a write signal to the memory unit strings. The source switch units are electrically connected to the memory string so that the memory strings receive a bias signal via the source switch unit. In a program mode, when a first bit switch unit of the bit switch units is turned on and a first memory strings receives the write signal through the first bit switch unit, the source switch units electrically connected to the other memory strings will be turned on.

公开(公告)号：US10978485B2

公开(公告)日：2021-04-13

申请号：US16749806

申请日：2020-01-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: H01L27/11597 ,  H01L23/528 ,  H01L27/11592 ,  H01L29/51 ,  H01L29/78 ,  G11C11/22

Abstract: A device based on 2T vertical ferroelectric memory cells includes a plurality of select gate lines in a first layer, and a plurality of word lines in a second layer, with a plurality of vertical channel structures disposed operably with the select gate lines and word lines. A vertical channel structure of a memory cell in the plurality is disposed orthogonally relative to a corresponding select gate line and a corresponding word line, and forms a channel for the vertical select transistor and the vertical ferroelectric memory transistor. Ferroelectric material is disposed at cross-points between the vertical channel structure and the corresponding word line. A gate dielectric material is disposed at cross-points between the vertical channel structure and the corresponding select gate line. A NOR architecture memory uses the 2T vertical ferroelectric memory cells.

公开(公告)号：US10777566B2

公开(公告)日：2020-09-15

申请号：US16037281

申请日：2018-07-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: G11C7/18 ,  H01L27/11556 ,  H01L27/06 ,  H01L27/108 ,  G11C16/04 ,  G11C11/4097 ,  H01L21/822 ,  H01L27/112 ,  G11C5/02 ,  G11C7/10 ,  G11C8/14 ,  H01L27/11582 ,  H01L27/1157

Abstract: A device comprises a 3D array of cells arranged for execution of a sum-of-products operation, the cells in the 3D array disposed in cross-points of a plurality of vertical lines and a plurality of horizontal lines, the cells having programmable conductances. A gate driver is coupled to gate lines which applies control gate voltages which in combination with the programmable conductances of the cells correspond to weights Wxyz of terms in the sum-of-products operation. An input driver applies voltages to cells in the array corresponding to input variables Xy. A sensing circuit senses a sum of currents from cells in the 3D array corresponding to the sum-of-products.

公开(公告)号：US10727243B1

公开(公告)日：2020-07-28

申请号：US16407319

申请日：2019-05-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Wei-Chen Chen

IPC: H01L27/115 ,  H01L27/11556 ,  H01L27/11526 ,  H01L27/11521 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/28 ,  H01L27/11568 ,  H01L27/11551

Abstract: A 3D memory device includes a multi-layers stacking structure having a plurality of conductive layers and insulating layers stacked in a staggered manner, at least one trench passing through the conductive layers and a plurality of recess regions extending into the conductive layers from the trench; a dielectric blocking strip lining sidewalls of the trench and the recess regions; a plurality of floating gates disposed in the recess regions and isolated from the conductive layers by the dielectric blocking strip; a dielectric strip overlies sidewalls of the floating gates exposed from the recess regions; a semiconductor strip disposed in the trench, insulated from the floating gates by the dielectric strip, and includes a first doping region, a second doping region and a channel region disposed between and connects to the first doping region and the second doping region, and overlapping with the floating gates.

公开(公告)号：US09524980B2

公开(公告)日：2016-12-20

申请号：US14637204

申请日：2015-03-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/768 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/1037 ,  H01L29/511 ,  H01L29/66742

Abstract: A memory device, which can be configured as a 3D NAND flash memory, includes a plurality of stacks of conductive strips, including even stacks and odd stacks having sidewalls. Some of the conductive strips in the stacks are configured as word lines. Data storage structures are disposed on the sidewalls of the even and odd stacks. Active pillars between corresponding even and odd stacks of conductive strips include even and odd semiconductor films connected at the bottom of the trench between the stacks, and have outside surfaces and inside surfaces. The outside surfaces contact the data storage structures on the sidewalls of the corresponding even and odd stacks forming a 3D array of memory cells; the inside surfaces are separated by an insulating structure that can include a gap. The semiconductor films can be thin-films having a U-shaped current path.

Abstract translation: 可以被配置为3D NAND闪速存储器的存储器件包括多个导体条的堆叠，包括偶数堆叠和具有侧壁的奇数堆叠。 堆叠中的一些导电条被配置为字线。 数据存储结构设置在偶数和奇数堆栈的侧壁上。 在相应的偶数和奇数个导体条之间的有源支柱包括连接在堆叠之间的沟槽底部的偶数和奇数半导体膜，并具有外表面和内表面。 外表面接触形成存储器单元的3D阵列的对应偶数和奇数堆叠的侧壁上的数据存储结构; 内表面由可以包括间隙的绝缘结构隔开。 半导体膜可以是具有U形电流路径的薄膜。

公开(公告)号：US09520485B2

公开(公告)日：2016-12-13

申请号：US14460328

申请日：2014-08-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L27/02 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04

CPC classification number: H01L29/66833 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/11514 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/42392 ,  H01L29/66

Abstract: A memory device configurable for independent double gate cells, storing multiple bits per cell, includes multilayer stacks of conductive strips configured as word lines. Active pillars are disposed between pairs of first and second stacks, each active pillar comprising a vertical channel structure extending from an underlying bounded conductive layer, a charge storage layer and an insulating layer. The insulating layer in a frustum of an active pillar contacts a first arcuate edge of a first conductive strip in a layer of the first stack and a second arcuate edge of a second conductive strip in a same layer of the second stack. The conductive strips can comprise a metal. The active pillar can be generally elliptical with a major axis parallel with the first and second conductive strips.

Abstract translation: 可独立的双门单元配置的存储器件，每个单元存储多个位，包括配置为字线的导电条的多层堆叠。 主动柱布置在成对的第一和第二堆叠之间，每个活性柱包括从下面的有界导电层，电荷存储层和绝缘层延伸的垂直沟道结构。 有源柱的截头锥体中的绝缘层与第二堆叠的同一层中的第一堆叠层中的第一导电条的第一弧形边缘和第二导电条的第二弧形边缘接触。 导电条可以包括金属。 主动柱通常为椭圆形，长轴与第一和第二导电条平行。