公开(公告)号：US10510423B2

公开(公告)日：2019-12-17

申请号：US15669785

申请日：2017-08-04

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Mark Fischer ,  Adam D. Johnson

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C11/22

Abstract: Methods, systems, and devices for techniques to mitigate disturbances of unselected memory cells in a memory array during an access operation are described. A shunt line may be formed between a plate of a selected memory cell and a digit line of the selected memory cell to couple the plate to the digit line during the access operation. A switching component may be positioned on the shunt line. The switching component may selectively couple the plate to the digit line based on instructions received from a memory controller. By coupling the plate to the digit line during the access operation, voltages resulting on the plate by changes in the voltage level of the digit line may be reduced in magnitude or may be altered in type.

公开(公告)号：US20190287601A1

公开(公告)日：2019-09-19

申请号：US16427851

申请日：2019-05-31

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22 ,  G11C11/56 ,  G11C13/00

Abstract: The present disclosure includes apparatuses, methods, and systems for current separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell having a ferroelectric material, and determining a data state of the memory cell by separating a first current output by the memory cell while the sensing voltage is being applied to the memory cell and a second current output by the memory cell while the sensing voltage is being applied to the memory cell, wherein the first current output by the memory cell corresponds to a first polarization state of the ferroelectric material of the memory cell and the second current output by the memory cell corresponds a second polarization state of the ferroelectric material of the memory cell.

公开(公告)号：US10388351B2

公开(公告)日：2019-08-20

申请号：US15691454

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Richard E. Fackenthal ,  Daniele Vimercati ,  Duane R. Mills

IPC: G11C29/00 ,  G11C11/22 ,  G06F11/10

Abstract: Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g., ferroelectric random access memory (FeRAM) may utilize wear leveling to extend life time of the memory devices by avoiding reliability issues due to a limited cycling capability. A wear-leveling pool, or number of cells used for a wear-leveling application, may be expanded by softening or avoiding restrictions on a source page and a destination page within a same section of memory array. In addition, error correction code may be applied when moving data from the source page to the destination page to avoid duplicating errors present in the source page.

公开(公告)号：US20190130955A1

公开(公告)日：2019-05-02

申请号：US16184480

申请日：2018-11-08

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Scott James Derner ,  Umberto Di Vincenzo ,  Christopher Johnson Kawamura ,  Eric S. Carman

IPC: G11C11/22

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. A positive voltage may be applied to a memory cell; and after a voltage of the digit line of the cell has reached a threshold, a negative voltage may be applied to cause the digit line voltages to center around ground before a read operation. In another example, a first voltage may be applied to a memory cell and then a second voltage that is equal to an inverse of the first voltage may be applied to a reference capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a read operation.

公开(公告)号：US10248592B2

公开(公告)日：2019-04-02

申请号：US15225562

申请日：2016-08-01

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Daniele Vimercati

IPC: G06F12/00 ,  G06F13/24 ,  G11C5/06 ,  G11C7/22 ,  G11C13/00 ,  G06F3/06 ,  G06F12/02

Abstract: Subject matter disclosed herein relates to read and write processes of a memory device.

公开(公告)号：US10153020B1

公开(公告)日：2018-12-11

申请号：US15618393

申请日：2017-06-09

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/2275 ,  G11C11/2293

Abstract: Methods, systems, and devices for dual mode ferroelectric memory cell operation are described. A memory array or portions of the array may be variously operated in volatile and non-volatile modes. For example, a memory cell may operate in a non-volatile mode and then operate in a volatile mode following a command initiated by a controller while the cell is operating in the non-volatile mode. The memory cell may operate in the volatile mode and then operate in the non-volatile mode following a subsequent command. In some examples, one memory cell of the memory array may operate in the non-volatile mode while another memory cell of the memory array operates in the volatile mode.

公开(公告)号：US10083731B2

公开(公告)日：2018-09-25

申请号：US15067954

申请日：2016-03-11

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/22 ,  G11C11/221 ,  G11C11/2293

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be selected using a selection component that is in electronic communication with a sense amplifier and a ferroelectric capacitor of a ferroelectric memory cell. A voltage applied to the ferroelectric capacitor may be sized to increase the signal sensed during a read operation. The ferroelectric capacitor may be isolated from the sense amplifier during the read operation. This isolation may avoid stressing the ferroelectric capacitor which may otherwise occur due to the applied read voltage and voltage introduce by the sense amplifier during the read operation.

公开(公告)号：US09934837B2

公开(公告)日：2018-04-03

申请号：US15057914

申请日：2016-03-01

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Scott James Derner ,  Umberto Di Vincenzo ,  Christopher John Kawamura ,  Eric S. Carman

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2293

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. A positive voltage may be applied to a memory cell; and after a voltage of the digit line of the cell has reached a threshold, a negative voltage may be applied to cause the digit line voltages to center around ground before a read operation. In another example, a first voltage may be applied to a memory cell and then a second voltage that is equal to an inverse of the first voltage may be applied to a reference capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a read operation.

公开(公告)号：US20170352397A1

公开(公告)日：2017-12-07

申请号：US15173310

申请日：2016-06-03

Applicant: Micron Technology, Inc.

Inventor： Xinwei Guo ,  Daniele Vimercati

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2275

Abstract: Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a ferroelectric memory cell or cells is described. The scheme employs a charge mirror to extract the full charge difference between the two states of a selected memory cell. The charge mirror may transfer the memory cell polarization charge to an amplification capacitor. The signal on the amplification capacitor may then be compared with a reference voltage to detect the logic state of the memory cell.

公开(公告)号：US09418735B2

公开(公告)日：2016-08-16

申请号：US14679745

申请日：2015-04-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Efrem Bolandrina ,  Daniele Vimercati

IPC: G11C7/00 ,  G11C13/00 ,  G11C11/16

CPC classification number: G11C13/0033 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/79

Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping element, and control circuit. The memory cell and clamping element can be both coupled to a digit line. The control circuit can be configured to cause the clamping element to clamp the voltage of the digit line for a period of time while the digit line driver is caused to bias the digit line at a voltage level sufficient to enable selection of the memory cell. In addition, the control circuit can be configured to cause the access line driver to bias an access line coupled to memory cell when the voltage of the digit line is at the voltage level sufficient to enable selection of the memory cell.