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    Vertical memory strings, and vertically-stacked structures
    71.
    发明授权
    Vertical memory strings, and vertically-stacked structures 有权

    公开(公告)号：US10121906B2

    公开(公告)日：2018-11-06

    申请号：US15467765

    申请日：2017-03-23

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins

    IPC: H01L29/788 ,  H01L21/28 ,  H01L21/02 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L29/423 ,  H01L29/51

    Abstract: Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. An electrically insulative panel is formed within the trench. Some sections of the panel are removed to form openings. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Charge blocking material and charge-storage material is formed within the cavities. Channel material is formed within the openings and is spaced from the charge-storage material by gate dielectric material. Some embodiments include semiconductor constructions, and some embodiments include methods of forming vertically-stacked structures.

    Semiconductor constructions
    75.
    发明授权
    Semiconductor constructions 有权
    半导体结构

    公开(公告)号：US09105737B2

    公开(公告)日：2015-08-11

    申请号：US13735908

    申请日：2013-01-07

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins

    IPC: H01L29/788 ,  H01L29/66 ,  H01L29/792 ,  H01L21/336 ,  H01L21/28 ,  H01L27/115

    CPC classification number: H01L29/7889 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/511 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7926

    Abstract: Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. An electrically insulative panel is formed within the trench. Some sections of the panel are removed to form openings. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Charge blocking material and charge-storage material is formed within the cavities. Channel material is formed within the openings and is spaced from the charge-storage material by gate dielectric material. Some embodiments include semiconductor constructions, and some embodiments include methods of forming vertically-stacked structures.

    Abstract translation: 一些实施例包括形成垂直存储器串的方法。 形成沟槽以延伸通过交替导电水平和电绝缘水平的堆叠。 在沟槽内形成电绝缘面板。 去除面板的一些部分以形成开口。 每个开口具有沿堆叠的第一对相对侧，并且具有沿面板的剩余部分的第二对相对侧。 腔形成为沿着开口的第一对相对侧延伸到导电水平。 在空腔内形成电荷阻挡材料和电荷储存材料。 通道材料形成在开口内并且通过栅极电介质材料与电荷存储材料间隔开。 一些实施例包括半导体结构，并且一些实施例包括形成垂直堆叠结构的方法。

    Patterned bases, and patterning methods
    76.
    发明授权
    Patterned bases, and patterning methods 有权
    图案基底和图案化方法

    公开(公告)号：US08921034B2

    公开(公告)日：2014-12-30

    申请号：US13631068

    申请日：2012-09-28

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins

    IPC: G03F7/00 ,  H01L27/115

    CPC classification number: H01L21/3086 ,  G03F7/0035 ,  H01L21/0337 ,  H01L21/3088 ,  H01L27/10894 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/0657

    Abstract: Some embodiments include methods of patterning a base. First and second masking features are formed over the base. The first and second masking features include pedestals of carbon-containing material capped with silicon oxynitride. A mask is formed over the second masking features, and the silicon oxynitride caps are removed from the first masking features. Spacers are formed along sidewalls of the first masking features. The mask and the carbon-containing material of the first masking features are removed. Patterns of the spacers and second masking features are transferred into one or more materials of the base to pattern said one or more materials. Some embodiments include patterned bases.

    Abstract translation: 一些实施例包括图案化基底的方法。 在基底上形成第一和第二掩蔽特征。 第一和第二掩模特征包括用氮氧化硅覆盖的含碳材料的基座。 在第二掩蔽特征上形成掩模，并且从第一掩蔽特征中去除氧氮化硅帽。 间隔件沿着第一掩蔽特征的侧壁形成。 去除掩模和第一掩蔽特征的含碳材料。 间隔物和第二掩蔽特征的图案被转移到基底的一种或多种材料中以图案化所述一种或多种材料。 一些实施例包括图案化基底。

    Semiconductor Constructions
    77.
    发明申请
    Semiconductor Constructions 有权
    半导体建筑

    公开(公告)号：US20140306323A1

    公开(公告)日：2014-10-16

    申请号：US13860427

    申请日：2013-04-10

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Chris Larsen ,  Alex J. Schrinsky ,  John D. Hopkins ,  Matthew King

    IPC: H01L29/06

    CPC classification number: H01L29/0657 ,  H01L21/743 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0692

    Abstract: Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X.

    Abstract translation: 一些实施例包括具有通过至少一个虚拟突起彼此间隔开的两个台面的半导体材料的半导体结构。 虚拟突起具有沿X的横截面的宽度，并且台面具有至少3X的横截面的宽度。 一些实施例包括具有存储器阵列区域和与存储器阵列区域相邻的外围区域的半导体结构。 周边区域内的半导体材料被图案化成两个相对较宽的台面，其彼此间隔开至少一个较窄的突起。 相对窄的突起具有沿X的横截面的宽度，并且相对宽的台面具有至少3X的横截面的宽度。

    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    78.
    发明申请
    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20250166704A1

    公开(公告)日：2025-05-22

    申请号：US19027291

    申请日：2025-01-17

    Applicant: Micron Technology, Inc.

    Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Collin Howder ,  Jordan D. Greenlee

    IPC: G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. The lower portion comprises an upper second tier comprising insulative material. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion. Channel-material strings are formed that extend through the upper portion to the lower portion. Horizontally-elongated lines are formed in the upper second tier longitudinally-along opposing lateral edges of the memory-block regions. Material of the lines is of different composition from that of the insulative material in the upper second tier that is laterally-between the lines. Horizontally-elongated trenches are formed into the stack that are individually between immediately-laterally-adjacent of the memory-block regions and that extend through the upper portion to the lower portion. Other embodiments, including structure independent of method, are disclosed.

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