公开(公告)号：US07838907B2

公开(公告)日：2010-11-23

申请号：US12141978

申请日：2008-06-19

申请人： Masaki Shiraishi

发明人： Masaki Shiraishi

IPC分类号： H01L27/06 ,  H01L27/095 ,  H01L29/778 ,  H01L21/8232 ,  H01L21/338

CPC分类号： H01L27/0605 ,  H01L27/0629 ,  H01L27/0688 ,  H01L29/2003 ,  H01L29/7787 ,  H01L29/861 ,  H01L2224/0603 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2924/13055 ,  H01L2924/00

摘要： In a semiconductor device in which a diode and a high electron mobility transistor are incorporated in the same semiconductor chip, a compound semiconductor layer of the high electron mobility transistor is formed on a main surface (first main surface) of a semiconductor substrate of the diode, and an anode electrode of the diode is electrically connected to an anode region via a conductive material embedded in a via hole (hole) reaching a p+ region which is the anode region of the main surface of the semiconductor substrate from a main surface of the compound semiconductor layer.

摘要翻译： 在二极管和高电子迁移率晶体管并入同一半导体芯片的半导体器件中，高电子迁移率晶体管的化合物半导体层形成在二极管的半导体衬底的主表面（第一主表面）上 ，并且二极管的阳极电极经由嵌入到通孔（孔）中的导电材料电连接到从半导体衬底的主表面到达作为半导体衬底的主表面的阳极区域的p +区域的导电材料 化合物半导体层。

公开(公告)号：US20090212358A1

公开(公告)日：2009-08-27

申请号：US12385979

申请日：2009-04-27

申请人： Masaki Shiraishi ,  Yoshito Nakazawa

发明人： Masaki Shiraishi ,  Yoshito Nakazawa

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L21/26586 ,  H01L24/05 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2224/05552 ,  H01L2224/0603 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

摘要： A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 μm or less, a p− type semiconductor region is formed to a depth so as not to cover the bottom of the groove, and a p-type semiconductor region higher in impurity concentration than the p−type semiconductor region is formed under a n+type semiconductor region serving as a source region of the trench gate type power MISFET, causing the p-type semiconductor region to serve as a punch-through stopper layer of the trench gate type power MISFET.

摘要翻译： 提供了一种降低导通电阻的技术，并且相对于沟槽栅型功率MISFET实现了穿通的防止。 输入电容和反馈电容通过形成其中形成栅电极的沟槽减小，使得其深度为约1μm或更小的深度，p型半导体区域形成为不覆盖的深度 在作为沟道栅极型功率MISFET的源极区域的n +型半导体区域的下方形成杂质浓度高于p型半导体区域的p型半导体区域的p型半导体区域， 型半导体区域用作沟槽栅型功率MISFET的穿通阻挡层。

公开(公告)号：US20090033377A1

公开(公告)日：2009-02-05

申请号：US12170472

申请日：2008-07-10

申请人： Takayuki Hashimoto ,  Takashi Hirao ,  Masaki Shiraishi

发明人： Takayuki Hashimoto ,  Takashi Hirao ,  Masaki Shiraishi

IPC分类号： H03K3/012

CPC分类号： H02M3/07 ,  H02M1/08 ,  H02M7/5387 ,  H02M2003/071

摘要： A drive circuit for driving a semiconductor element is equipped with: a first switch connected to a positive side of a DC power supply; a second switch connected to the other terminal of the first switch and to a negative side of the DC power supply; a third switch connected to the positive side of the DC power supply; a fourth switch connected to the other terminal of the third switch; a fifth switch connected to the other terminal of the fourth switch and to the negative side of the DC power supply; and a capacitor connected to the other terminal of the first switch and to the other terminal of the fourth switch. A gate of the semiconductor element is connected to the other terminal of said third switch; and a source of the semiconductor element is connected to the negative side of the DC power supply.

摘要翻译： 用于驱动半导体元件的驱动电路配备有：连接到直流电源的正侧的第一开关; 连接到第一开关的另一个端子和直流电源的负极的第二开关; 连接到直流电源的正极的第三开关; 连接到第三开关的另一个端子的第四开关; 连接到第四开关的另一个端子和直流电源的负极的第五开关; 以及电容器，连接到第一开关的另一端子和第四开关的另一端子。 半导体元件的栅极连接到所述第三开关的另一个端子; 并且半导体元件的源极连接到直流电源的负极侧。

公开(公告)号：US20090026830A1

公开(公告)日：2009-01-29

申请号：US10584190

申请日：2005-06-01

申请人： Masaki Shiraishi ,  Tadashi Imamura ,  Yoshiaki Kimura ,  Kenji Maki

发明人： Masaki Shiraishi ,  Tadashi Imamura ,  Yoshiaki Kimura ,  Kenji Maki

IPC分类号： B60B9/12 ,  B23P17/00

CPC分类号： B60B9/12 ,  Y10T29/49503

摘要： An elastic wheel comprises a rim for mounting a tire, a disk to be fixed to an axle, and a connecting apparatus for connecting elastically between the rim and disk, the apparatus comprising a pair of axially spaced internal flanges each provided on an inner circumference side of the rim and extending circumferentially, an external flange provided on a radially outer portion of the disk, the external flange disposed in a space between the internal flanges with an axial gap on its both sides and extending circumferentially, a pair of rubber dampers each disposed in the axial gap and connecting between the internal and external flanges, wherein each internal flange is provided on its axially inner side with a first groove, the external flange is provided on its both sides with a second groove so as to face each first groove, axial ends of each damper are inserted into the first and second grooves, and a radial gap is provided between the external flange and the inner circumference side of the rim in the space.

摘要翻译： 弹性轮包括用于安装轮胎的轮辋，待固定到车轴的盘和用于弹性地连接在轮辋和盘之间的连接装置，该装置包括一对轴向隔开的内凸缘，每个内凸缘设置在内周侧 所述外凸缘设置在所述盘的径向外部部分上，所述外凸缘设置在所述内凸缘之间的空间中，在其两侧具有轴向间隙并沿周向延伸;一对橡胶阻尼器，每个设置在所述外凸缘 在轴向间隙和内外凸缘之间的连接处，其中每个内凸缘在其轴向内侧设置有第一凹槽，外凸缘在其两侧设置有第二凹槽，以面对每个第一凹槽， 每个阻尼器的轴向端部插入到第一和第二槽中，并且在外部凸缘和内周侧之间设置径向间隙 在空间里的边缘。

公开(公告)号：US20070013000A1

公开(公告)日：2007-01-18

申请号：US11484610

申请日：2006-07-12

申请人： Masaki Shiraishi

发明人： Masaki Shiraishi

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H02M3/1588

摘要： In a low withstand voltage vertical trench MOSFET having an SJ structure, an N type epitaxial layer which is a current path and a trench structure which extends from a semiconductor surface into the N type epitaxial layer are provided, and a floating P type region is formed in a portion of the N type epitaxial layer positioned below the trench structure. The P type region is formed below the trench structure by ion-implanting P type impurity ions. By forming the P type region below a fine trench gate through ion-implantation, energy for ion-implantation can be reduced, and a fine SJ structure can be fabricated. Accordingly, a device structure which allow formation of a fine SJ structure in a low withstand voltage power MOSFET and a manufacturing method of the same can be provided.

摘要翻译： 在具有SJ结构的低耐压垂直沟槽MOSFET中，提供作为电流路径的N型外延层和从半导体表面延伸到N型外延层的沟槽结构，形成浮动P型区域 在位于沟槽结构下方的N型外延层的一部分。 通过离子注入P型杂质离子，在沟槽结构的下方形成P型区域。 通过离子注入形成细沟槽栅极以下的P型区域，可以减少离子注入的能量，能够制造精细的SJ结构。 因此，可以提供允许在低耐压功率MOSFET中形成精细SJ结构的器件结构及其制造方法。

公开(公告)号：US07130748B2

公开(公告)日：2006-10-31

申请号：US10481754

申请日：2002-07-16

申请人： Masahiko Ueda ,  Kazuyoshi Miyamoto ,  Masaki Shiraishi

发明人： Masahiko Ueda ,  Kazuyoshi Miyamoto ,  Masaki Shiraishi

IPC分类号： G01L1/00 ,  G06G7/48

CPC分类号： G06F17/5018

摘要： A simulation method includes the step of momently measuring a value of each of a strain, a strain speed, and a stress generated in the viscoelastic material, deriving time history data of a viscous drag, the strain speed and the stress, thereby deriving a relationship among the strain, the strain speed, and the viscous drag and setting the product as a product model whose performance is analyzed; inputting the relationship to the product model; and computing a stress and strain of a deviation component by using a deviation main strain and a deviation main strain speed converted from an entire coordinate system into a main strain coordinate system and a main strain speed coordinate system respectively to thereby conduct a simulation in consideration of a change of the viscous drag which occurs in dependence of a variation of the strain and the strain speed.

摘要翻译： 模拟方法包括以下步骤：简单地测量在粘弹性材料中产生的应变，应变速度和应力中的每一个的值，导出粘滞阻力，应变速度和应力的时间历史数据，从而导出关系 在应变，应变速度和粘滞阻力之间，将产品设置为性能分析的产品模型; 输入与产品型号的关系; 以及通过使用从整个坐标系转换成主应变坐标系和主应变速度坐标系的偏差主应变和偏差主应变速度来分别计算偏差分量的应力和应变，从而进行考虑 根据应变和应变速度的变化而发生的粘性阻力的变化。

公开(公告)号：US20060175627A1

公开(公告)日：2006-08-10

申请号：US11347290

申请日：2006-02-06

申请人： Masaki Shiraishi

发明人： Masaki Shiraishi

IPC分类号： H01L33/00 ,  H01L29/22

CPC分类号： H01L29/7787 ,  H01L23/49575 ,  H01L25/16 ,  H01L29/2003 ,  H01L29/7813 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/1588 ,  Y02B70/1466 ,  Y02B70/1483 ,  H01L2924/00014 ,  H01L2924/00

摘要： A power supply includes a non-isolated DC-DC converter for use in a power source system having a high side switch and a low side switch, in which HEMT or HFET or gallium nitride device with low capacity and low on-resistance is used for the high side switch and a vertical power MOSFET of silicon device with low on-resistance is used for the low side switch.

摘要翻译： 电源包括用于具有高侧开关和低侧开关的电源系统中的非隔离DC-DC转换器，其中使用具有低容量和低导通电阻的HEMT或HFET或氮化镓器件用于 低侧开关使用高侧开关和具有低导通电阻的硅器件的垂直功率MOSFET。

公开(公告)号：US07066018B2

公开(公告)日：2006-06-27

申请号：US10832289

申请日：2004-04-27

申请人： Kazuyoshi Miyamoto ,  Masaki Shiraishi

发明人： Kazuyoshi Miyamoto ,  Masaki Shiraishi

IPC分类号： E01C23/00

CPC分类号： G06F17/5095 ,  B60C11/0318 ,  B60C19/00 ,  B60C99/006 ,  G01M17/02 ,  G06F17/5018

摘要： A method of simulating a tire rolling on a road includes modeling the tire in finite elements to make a tire model; modeling the surface of the road in finite elements to make a road model; executing a simulation in which the tire model is made to roll on the road model at a predetermined speed; and obtaining information about the tire model. The speed of the tire model is varied by repeating an increase and a decrease based on a predetermined reference speed.

摘要翻译： 模拟轮胎在道路上滚动的方法包括以有限元模拟轮胎以制造轮胎模型; 以有限元建模道路表面，形成道路模型; 执行轮胎模型以预定速度在道路模型上滚动的模拟; 并获取有关轮胎模型的信息。 通过基于预定的参考速度重复增加和减少来改变轮胎模型的速度。

公开(公告)号：US07019362B2

公开(公告)日：2006-03-28

申请号：US10781704

申请日：2004-02-20

申请人： Kozo Sakamoto ,  Takayuki Iwasaki ,  Masaki Shiraishi

发明人： Kozo Sakamoto ,  Takayuki Iwasaki ,  Masaki Shiraishi

IPC分类号： H01L29/76

CPC分类号： H01L24/02 ,  H01L29/0692 ,  H01L2224/0401 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： The gate resistance of a power MOSFET in a semiconductor chip is reduced and the reliability and yield of the gate of the power MOSFET are improved The semiconductor chip includes two or more control electrode pads functioning as control electrodes for a power semiconductor device formed within a semiconductor chip. The two or more control electrode pads are distributed within the periphery of the gate area of the power semiconductor device such that the gate resistance of the power semiconductor device can be reduced. The two or more control electrode pads are connected via bumps or a conductive bonding material to an electrode layer of a multilayer circuit board disposed outside the semiconductor chip.

摘要翻译： 半导体芯片中的功率MOSFET的栅极电阻降低，并且功率MOSFET的栅极的可靠性和产量得到改善。半导体芯片包括用作形成在半导体内的功率半导体器件的控制电极的两个或更多个控制电极焊盘 芯片。 两个以上的控制电极焊盘分布在功率半导体器件的栅极区域的周围，使得能够降低功率半导体器件的栅极电阻。 两个以上的控制电极焊盘通过凸块或导电接合材料连接到设置在半导体芯片外部的多层电路板的电极层。

公开(公告)号：US20050029584A1

公开(公告)日：2005-02-10

申请号：US10886041

申请日：2004-07-08

申请人： Masaki Shiraishi ,  Yoshito Nakazawa

发明人： Masaki Shiraishi ,  Yoshito Nakazawa

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49

CPC分类号： H01L29/7811 ,  H01L21/26586 ,  H01L24/05 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2224/05552 ,  H01L2224/0603 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

摘要： A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 μm or less, a p−type semiconductor region is formed to a depth so as not to cover the bottom of the groove, and a p-type semiconductor region higher in impurity concentration than the p−type semiconductor region is formed under a n+type semiconductor region serving as a source region of the trench gate type power MISFET, causing the p-type semiconductor region to serve as a punch-through stopper layer of the trench gate type power MISFET.

摘要翻译： 提供了一种降低导通电阻的技术，并且相对于沟槽栅型功率MISFET实现了穿通的防止。 输入电容和反馈电容通过形成栅极形成的沟槽而减小，使得其深度为1μm或更小的深度，形成深度不高于 覆盖凹槽的底部，并且在用作沟槽栅型功率MISFET的源极区域的+ +型半导体区域之下形成杂质浓度高于p型半导体区域的p型半导体区域， 导致p型半导体区域用作沟槽栅型功率MISFET的穿通阻挡层。