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124 条记录 (耗时 0.026 秒)

    Method of producing resin composition containing inorganic filler
    73.
    发明授权
    Method of producing resin composition containing inorganic filler 失效
    含有无机填料的树脂组合物的制造方法

    公开(公告)号：US5932634A

    公开(公告)日：1999-08-03

    申请号：US836913

    申请日：1997-05-23

    申请人： Teruo Hosokawa ,  Hirofumi Inoue ,  Yoshihiro Moteki

    发明人： Teruo Hosokawa ,  Hirofumi Inoue ,  Yoshihiro Moteki

    IPC分类号： C08K7/00 ,  C08K9/04 ,  C08K3/10 ,  C08K3/34

    CPC分类号： C08K7/00 ,  C08K9/04

    摘要： A method of producing a resin composition containing an inorganic filler is disclosed, wherein organic cations having a steric hindrance structure are brought into contact with a layered mineral with an equivalent area per unit charge on the layer surface of 40-150 .ANG..sup.2 /charge, then brought into contact with a thermoplastic resin having a solubility parameter of at least 9.5 �cal/cm.sup.3 !.sup.1/2, so as to disperse the layered mineral inside the resin at the molecular level. The resin compositions obtained by this production method have excellent rigidity, heat resistance and impact resistance, and are suitable for use in fields such as, for example, automobiles, household electronic parts, construction materials and industrial materials.

    摘要翻译： PCT No.PCT / JP96 / 02754 Sec。 371日期1997年5月23日 102（e）日期1997年5月23日PCT提交1996年9月25日PCT公布。 公开号WO97 / 11998 日本1997年4月3日公开了含有无机填料的树脂组合物的制造方法，其中具有空间位阻结构的有机阳离子与层表面上的每单位电荷的等效面积接触40-150 ANGSTROM 2 /充电，然后与溶解度参数为至少9.5 [cal / cm3] + E，fra 1/2 + EE的热塑性树脂接触，以便将层状矿物分散在树脂中的分子水平 。 通过该制造方法获得的树脂组合物具有优异的刚性，耐热性和耐冲击性，并且适用于例如汽车，家用电子部件，建筑材料和工业材料等领域。

    Nonvolatile semiconductor memory device
    75.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08391082B2

    公开(公告)日：2013-03-05

    申请号：US13099540

    申请日：2011-05-03

    申请人： Hiroyuki Nagashima ,  Hirofumi Inoue

    发明人： Hiroyuki Nagashima ,  Hirofumi Inoue

    IPC分类号： G11C7/10

    CPC分类号： G11C13/0069 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1075 ,  G11C7/22 ,  G11C8/16 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0061 ,  G11C13/0097 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2216/24

    摘要： A nonvolatile semiconductor memory device comprises a cell array including plural MATs (unit cell arrays) arranged in matrix, each MAT containing a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, each memory cell containing an electrically erasable programmable variable resistive element of which resistance is stored in a non-volatile manner as data; and a plurality of write/erase circuits connected to the MATs and operative to execute data write or erase to the memory cells inside the MATs in accordance with input data. A part of the plurality of write/erase circuits writes data to memory cells inside a corresponding MAT while another part of the plurality of write/erase circuits erases data from memory cells inside a corresponding MAT at the same time.

    摘要翻译： 一种非易失性半导体存储器件，包括一个单元阵列，该单元阵列包括矩阵排列的多个MAT（单元阵列），每个MAT包含多条第一线，与该多条第一线交叉的多条第二线，以及多条存储单元 两行之间的第一和第二行的交点，每个存储单元包含以电阻作为数据以非易失性方式存储的电可擦除可编程可变电阻元件; 以及多个写入/擦除电路，连接到MAT，并根据输入数据对MAT内的存储单元执行数据写入或擦除。 多个写/擦除电路的一部分将数据写入相应MAT内的存储单元，而多个写/擦除电路的另一部分同时从相应MAT内的存储单元擦除数据。

    Non-volatile semiconductor memory device including memory cells with a variable resistor
    76.
    发明授权
    Non-volatile semiconductor memory device including memory cells with a variable resistor 有权
    包括具有可变电阻器的存储单元的非易失性半导体存储器件

    公开(公告)号：US08391048B2

    公开(公告)日：2013-03-05

    申请号：US12846198

    申请日：2010-07-29

    申请人： Reika Ichihara ,  Takayuki Tsukamoto ,  Kenichi Murooka ,  Hirofumi Inoue ,  Hiroshi Kanno

    发明人： Reika Ichihara ,  Takayuki Tsukamoto ,  Kenichi Murooka ,  Hirofumi Inoue ,  Hiroshi Kanno

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0061 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0092

    摘要： A non-volatile semiconductor memory device according to an aspect of embodiments of the present invention includes a memory cell array including: multiple first wirings; multiple second wirings crossing the multiple first wirings; and multiple electrically rewritable memory cells respectively arranged at intersections of the first wirings and the second wirings, and each formed of a variable resistor which stores a resistance value as data in a non-volatile manner. The non-volatile semiconductor memory device according to an aspect of the embodiments of the present invention further includes a controller for selecting a given one of the memory cells, generating an erase pulse which is used for erasing data, and supplying the erase pulse to the selected memory cell. The erase pulse has a pulse width which is increased or decreased exponentially in accordance with an access path length to the selected memory cell.

    摘要翻译： 根据本发明的实施例的非易失性半导体存储器件包括：存储单元阵列，包括：多个第一布线; 多个第二布线穿过多个第一布线; 以及分别布置在第一布线和第二布线的交点处的多个电可重写存储器单元，并且每个由可变电阻器形成，其以非易失性方式存储电阻值作为数据。 根据本发明的实施例的一个方面的非易失性半导体存储器件还包括一个控制器，用于选择给定的一个存储单元，产生用于擦除数据的擦除脉冲，并将擦除脉冲提供给 选择的存储单元。 擦除脉冲具有根据到所选存储单元的访问路径长度指数地增加或减少的脉冲宽度。

    Nonvolatile semiconductor memory device including via-holes continuously formed through plural cell array layers
    78.
    发明授权
    Nonvolatile semiconductor memory device including via-holes continuously formed through plural cell array layers 有权
    包括通过多个单元阵列层连续形成的通孔的非易失性半导体存储器件

    公开(公告)号：US08183602B2

    公开(公告)日：2012-05-22

    申请号：US12275682

    申请日：2008-11-21

    申请人： Hideyuki Tabata ,  Eiji Ito ,  Hirofumi Inoue

    发明人： Hideyuki Tabata ,  Eiji Ito ,  Hirofumi Inoue

    IPC分类号： H01L23/52

    CPC分类号： H01L27/2481 ,  G11C13/00 ,  G11C13/0009 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines indifferent cell array layers.

    摘要翻译： 非易失性半导体存储器件包括半导体衬底; 形成在所述半导体衬底上的单元阵列块，并且包括多个堆叠的单元阵列层，每个堆叠的单元阵列层具有多个第一线，与所述多条第一线交叉的多个第二线，以及在所述第一和第二线的两个交点处连接的存储单元 线条 以及在单元阵列层的堆叠方向上延伸的多个通孔，以将每个单元阵列层中的第一或第二线分别连接到半导体基板。 通孔连续地形成在多个单元阵列层中，并且具有相同的下端位置和上端位置的多个通孔连接到第一或第二线不同的单元阵列层。

    Suspension system for vehicle
    79.
    发明授权
    Suspension system for vehicle 有权
    车辆悬挂系统

    公开(公告)号：US08103408B2

    公开(公告)日：2012-01-24

    申请号：US12091385

    申请日：2006-10-25

    申请人： Hirofumi Inoue ,  Takuhiro Kondo ,  Yoshihiro Suda

    发明人： Hirofumi Inoue ,  Takuhiro Kondo ,  Yoshihiro Suda

    IPC分类号： B60G17/015

    CPC分类号： F16F15/03 ,  B60G17/06 ,  B60G2202/42 ,  B60G2400/102 ,  B60G2400/104 ,  B60G2400/106 ,  B60G2400/204 ,  B60G2400/252 ,  B60G2400/41 ,  B60G2500/10 ,  B60G2800/012 ,  B60G2800/014

    摘要： In a system including four electromagnetic absorbers for respective four vehicle wheels, motor coils of two respective electromagnetic absorbers disposed corresponding to two diagonally located wheels are connected forming a closed loop including the coils. A generated damping force magnitude can be made different between an instance directions of respective movements of the diagonally located two wheels with respect to the vehicle body are the same, and an instance the directions are opposite each other. Each electromagnetic absorber includes a resistor cooperating with the corresponding coil forming a closed loop, and selectively establishes: a connected state in which one of the four coils and any of the other three coils are connected to form a closed loop; and a non-connected state in which the one of the four coils is not connected to any other coil. An appropriate vibration suppressing action is exhibited with respect to a coupled motion.

    摘要翻译： 在包括用于相应的四个车轮的四个电磁吸收器的系统中，连接两个对应于两个对角定位的车轮设置的两个相应的电磁吸收器的电机线圈，形成包括线圈的闭合回路。 在相对于车身的对角位置的两个车轮的各个运动的实例方向相同的情况下，可以使所产生的阻尼力大小不同，并且方向彼此相反。 每个电磁吸收器包括与形成闭环的相应线圈配合的电阻器，并且选择性地建立：连接状态，其中四个线圈中的一个线圈和任何其他三个线圈中的一个被连接以形成闭环; 以及四个线圈中的一个未连接到任何其它线圈的非连接状态。 相对于耦合运动而言，显示适当的振动抑制动作。

    SEMICONDUCTOR MEMORY DEVICE
    80.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20120012807A1

    公开(公告)日：2012-01-19

    申请号：US13182095

    申请日：2011-07-13

    申请人： Takeshi YAMAGUCHI ,  Hirofumi Inoue ,  Reika Ichihara ,  Takayuki Tsukamoto ,  Takashi Shigeoka ,  Katsuyuki Sekine ,  Shinya Aoki

    发明人： Takeshi YAMAGUCHI ,  Hirofumi Inoue ,  Reika Ichihara ,  Takayuki Tsukamoto ,  Takashi Shigeoka ,  Katsuyuki Sekine ,  Shinya Aoki

    IPC分类号： H01L45/00

    CPC分类号： H01L45/146 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/1233

    摘要： A semiconductor memory device in an embodiment comprises memory cells, each of the memory cells disposed between a first line and a second line and having a variable resistance element and a switching element connected in series. The variable resistance element includes a variable resistance layer configured to change in resistance value thereof between a low-resistance state and a high-resistance state. The variable resistance layer is configured by a transition metal oxide. A ratio of transition metal and oxygen configuring the transition metal oxide varies between 1:1 and 1:2 along a first direction directed from the first line to the second line.

    摘要翻译： 实施例中的半导体存储器件包括存储单元，每个存储单元设置在第一线和第二线之间，并且具有串联连接的可变电阻元件和开关元件。 可变电阻元件包括可变电阻层，其被配置为在低电阻状态和高电阻状态之间改变其电阻值。 可变电阻层由过渡金属氧化物构成。 构成过渡金属氧化物的过渡金属和氧的比例沿着从第一线指向第二线的第一方向在1:1和1:2之间变化。