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100 条记录 (耗时 0.046 秒)

    Air bridge process for forming air gaps
    72.
    发明授权
    Air bridge process for forming air gaps 有权
    用于形成气隙的气桥过程

    公开(公告)号：US06265321B1

    公开(公告)日：2001-07-24

    申请号：US09550264

    申请日：2000-04-17

    申请人： Simon Chooi ,  Mei-Sheng Zhou ,  Yi Xu

    发明人： Simon Chooi ,  Mei-Sheng Zhou ,  Yi Xu

    IPC分类号： H01L2100

    CPC分类号： H01L21/7682 ,  H01L21/76807

    摘要： A method for reducing RC delay in integrated circuits by lowering the dielectric constant of the intermetal dielectric material between metal interconnects or metal damascene interconnects is described. The dielectric constant of the intermetal dielectric is lowered by introducing air into the intermetal dielectric between metal interconnections. An air bridge comprising a porous material, preferably amorphous silicon, porous silicon oxide, or porous silsesquioxane, is deposited over a layer containing a reactive organic material. An oxygen plasma treatment or an anisotropic etching through the pores in the air bridge layer removes at least a portion of the reactive material, leaving air plugs within the intermetal dielectric.

    摘要翻译： 描述了通过降低金属互连或金属镶嵌互连之间的金属间电介质材料的介电常数来减小集成电路中的RC延迟的方法。 通过在金属互连之间的金属间电介质中引入空气来降低金属间电介质的介电常数。 包括多孔材料，优选非晶硅，多孔氧化硅或多孔倍半硅氧烷的空气桥被沉积在含有反应性有机材料的层上。 通过空气桥接层中的孔的氧等离子体处理或各向异性蚀刻去除至少一部分反应性材料，从而将空气塞留在金属间电介质内。

    Cleaning metal surfaces with alkyldione peroxides
    74.
    发明授权
    Cleaning metal surfaces with alkyldione peroxides 失效
    用烷基二酮过氧化物清洗金属表面

    公开(公告)号：US06132521A

    公开(公告)日：2000-10-17

    申请号：US467132

    申请日：1999-12-20

    申请人： Subhash Gupta ,  Simon Chooi ,  Mei Sheng Zhou ,  Paul Ho

    发明人： Subhash Gupta ,  Simon Chooi ,  Mei Sheng Zhou ,  Paul Ho

    IPC分类号： C11D3/20 ,  C11D3/39 ,  C23G5/032 ,  B08B3/04

    CPC分类号： C11D3/2072 ,  C11D3/2003 ,  C11D3/2093 ,  C11D3/3945 ,  C23G5/032 ,  Y10S134/902

    摘要： A method of cleaning elemental copper, cobalt, or nickel from the surface of equipment hardware without corroding or damaging the equipment parts and surfaces in the event of wafer breakage and non-wafer breakage is described. A solution includes an alkyldione peroxide, a stabilizing agent, and alcohols is used to oxidize the metal and form soluble complexes which are removed by the cleaning solution. Also, a alkyldione peroxide solution for cleaning elemental copper, cobalt, or nickel from the surface of equipment hardware in the event of wafer breakage and non-wafer breakage is provided.

    摘要翻译： 描述了从设备硬件表面清除元素铜，钴或镍的方法，而不会在晶片断裂和非晶片断裂的情况下腐蚀或损坏设备部件和表面。 溶液包括烷基二酮过氧化物，稳定剂，醇用于氧化金属并形成由清洗溶液除去的可溶性络合物。 此外，提供了在晶片断裂和非晶片断裂的情况下从设备硬件的表面清除元素铜，钴或镍的烷基二氧化碳过氧化物溶液。

    Chemical mechanical polish (CMP) endpoint detection by colorimetry
    75.
    发明授权
    Chemical mechanical polish (CMP) endpoint detection by colorimetry 失效
    化学机械抛光（CMP）通过比色法终点检测

    公开(公告)号：US6117777A

    公开(公告)日：2000-09-12

    申请号：US902847

    申请日：1997-07-30

    申请人： Mei-Sheng Zhou ,  Simon Chooi

    发明人： Mei-Sheng Zhou ,  Simon Chooi

    IPC分类号： B24B37/04 ,  B24B49/12 ,  H01L21/3105 ,  H01L21/66 ,  H01L21/00

    CPC分类号： B24B37/013 ,  B24B37/042 ,  B24B49/12 ,  H01L21/31053 ,  H01L22/26

    摘要： A method for fabricating a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a planarizable layer. The planarizable layer has a lower residual portion of the planarizable layer and an upper removable portion of the planarizable layer, where one of the lower residual portion of the planarizable layer and the upper removable portion of the planarizable layer has a colorant incorporated therein. The colorant is positioned at a location which assists in monitoring and controlling an endpoint of a chemical mechanical polish (CMP) planarizing method employed in planarizing the planarizable layer. There is then planarized through the chemical mechanical polish (CMP) planarizing method the planarizable layer while employing the colorant concentration to determine the endpoint of the chemical mechanical polish (CMP) planarizing method.

    摘要翻译： 一种用于制造微电子制造的方法。 首先提供了在微电子制造中使用的衬底。 然后在衬底上形成可平面化的层。 可平面化层具有可平坦化层的较低残余部分和可平面化层的上部可去除部分，其中可平面化层的下部剩余部分和可平面化层的上部可去除部分中的一个具有并入其中的着色剂。 着色剂位于有助于监测和控制用于平坦化可平面化层的化学机械抛光（CMP）平面化方法的端点的位置。 然后通过化学机械抛光（CMP）平面化方法将平坦化层平坦化，同时使用着色剂浓度来确定化学机械抛光（CMP）平面化方法的终点。

    Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion
    76.
    发明授权
    Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion 有权
    使用反向阻挡金属方案形成铜镶嵌互连以消除铜扩散的方法

    公开(公告)号：US6040243A

    公开(公告)日：2000-03-21

    申请号：US398292

    申请日：1999-09-20

    申请人： Jianxun Li ,  Simon Chooi ,  Mei-Sheng Zhou

    发明人： Jianxun Li ,  Simon Chooi ,  Mei-Sheng Zhou

    IPC分类号： H01L21/768 ,  H01L21/44

    CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76831

    摘要： A method of fabricating damascene vias has been achieved. Diffusion of copper into dielectric layers due to overetch of the passivation layer is eliminated by a barrier layer. The method can be used to form dual damascene interconnects. Copper traces through an isolation layer are provided overlying a semiconductor substrate. A passivation layer is deposited overlying the copper traces and the isolation layer. A dielectric layer is deposited. A cap layer is deposited. The cap layer and the dielectric layer are patterned to expose the top surface of the passivation layer and to form trenches for the damascene vias. A barrier layer is deposited overlying the passivation layer, the dielectric layer, and the cap layer. The barrier layer is etched though to expose the top surfaces of the cap layer and the passivation layer. The barrier layer isolates the sidewalls of the trenches. The passivation layer is etched through to complete damascene vias. The barrier layer prevents copper sputtering onto the dielectric layer during the step of etching through the passivation layer.

    摘要翻译： 已经实现了制造大马士革过孔的方法。 通过阻挡层消除由于钝化层的过蚀刻而将铜扩散到电介质层中。 该方法可用于形成双镶嵌互连。 通过隔离层的铜迹线设置在半导体衬底上。 沉积在铜迹线和隔离层上的钝化层。 沉积介电层。 沉积盖层。 将盖层和电介质层图案化以暴露钝化层的顶表面并形成用于大马士革过孔的沟槽。 覆盖钝化层，电介质层和覆盖层的阻挡层被沉积。 蚀刻阻挡层以暴露盖层和钝化层的顶表面。 阻挡层隔离沟槽的侧壁。 蚀刻钝化层以完成大马士革过孔。 在蚀刻通过钝化层的步骤期间，阻挡层防止铜溅射到电介质层上。

    Method of fabricating a twin hammer tree shaped capacitor structure for a dram device
    77.
    发明授权
    Method of fabricating a twin hammer tree shaped capacitor structure for a dram device 失效
    制造用于电容器的双锤树形电容器结构的方法

    公开(公告)号：US5792692A

    公开(公告)日：1998-08-11

    申请号：US912323

    申请日：1997-08-18

    申请人： Jian-Xun Li ,  Simon Chooi ,  Mei-Sheng Zhou

    发明人： Jian-Xun Li ,  Simon Chooi ,  Mei-Sheng Zhou

    IPC分类号： H01L21/02 ,  H01L21/311 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

    CPC分类号： H01L27/10852 ,  H01L21/31116 ,  H01L27/10817 ,  H01L28/87 ,  H01L28/91 ,  H01L28/88

    摘要： A process for fabricating a large surface area, storage node structure, for a DRAM device, has been developed. The storage node structure is comprised of a lower level polysilicon structure, exhibiting a "twin hammer tree" shape, and connected to an upper polysilicon level, exhibiting a "branch" type shape. The fabrication process used to create this storage node structure, features various deposition procedures, used for insulator and polysilicon layers, and various anisotropic and isotropic, dry etch procedures, as well as wet etch procedures, used for creation of the "twin hammer tree" shaped structure.

    摘要翻译： 已经开发了用于制造用于DRAM器件的大表面积，存储节点结构的工艺。 存储节点结构包括呈现“双锤树”形状的较低级多晶硅结构，并连接到上多晶硅层，呈现“分支”型形状。 用于创建这种存储节点结构的制造工艺，具有用于绝缘体和多晶硅层的各种沉积工艺以及用于创建“双锤树”的各种各向异性和各向同性的干蚀刻工艺以及湿式蚀刻工艺， 形结构。