公开(公告)号：US07409520B2

公开(公告)日：2008-08-05

申请号：US11042692

申请日：2005-01-25

申请人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Gordon Taylor Davis ,  Harm Peter Hofstee ,  Fabrice Jean Verplanken ,  Colin Beaton Verrilli

发明人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Gordon Taylor Davis ,  Harm Peter Hofstee ,  Fabrice Jean Verplanken ,  Colin Beaton Verrilli

IPC分类号： G06F12/00

CPC分类号： G06F9/3851 ,  G06F9/3802 ,  G06F9/4843

摘要： Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.

摘要翻译： 公开了在多线程数字处理器的流水线中分发线程指令的系统和方法。 更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。 如果要选择的线程无法执行，则选择补充线程执行。

公开(公告)号：US07392511B2

公开(公告)日：2008-06-24

申请号：US10670824

申请日：2003-09-25

申请人： Daniel Alan Brokenshire ,  Harm Peter Hofstee ,  Barry L Minor ,  Mark Richard Nutter

发明人： Daniel Alan Brokenshire ,  Harm Peter Hofstee ,  Barry L Minor ,  Mark Richard Nutter

IPC分类号： G06F9/45

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A program is into at least two object files: one object file for each of the supported processor environments. During compilation, code characteristics, such as data locality, computational intensity, and data parallelism, are analyzed and recorded in the object file. During run time, the code characteristics are combined with runtime considerations, such as the current load on the processors and the size of the data being processed, to arrive at an overall value. The overall value is then used to determine which of the processors will be assigned the task. The values are assigned based on the characteristics of the various processors. For example, if one processor is better at handling intensive computations against large streams of data, programs that are highly computationally intensive and process large quantities of data are weighted in favor of that processor. The corresponding object is then loaded and executed on the assigned processor.

摘要翻译： 一个程序进入至少两个对象文件：一个对象文件，用于每个受支持的处理器环境。 在编译过程中，将数据位置，计算强度和数据并行等代码特征分析并记录在目标文件中。 在运行时间期间，代码特征与运行时考虑相结合，例如处理器上的当前负载和正在处理的数据的大小，以达到总体值。 然后，总体值用于确定哪些处理器将被分配任务。 这些值基于各种处理器的特性分配。 例如，如果一个处理器更好地处理针对大量数据流的密集计算，则高度计算密集的程序和处理大量数据的程序对该处理器进行加权。 然后在分配的处理器上加载和执行相应的对象。

公开(公告)号：US07389419B2

公开(公告)日：2008-06-17

申请号：US10733935

申请日：2003-12-10

申请人： Daniel Alan Brokenshire ,  Harm Peter Hofstee ,  Mohammad Peyravian

发明人： Daniel Alan Brokenshire ,  Harm Peter Hofstee ,  Mohammad Peyravian

IPC分类号： H04L9/00

CPC分类号： H04L9/3242

摘要： The present invention provides for authenticating a message. A security function is performed upon the message. The message is sent to a target. The output of the security function is sent to the target. At least one publicly known constant is sent to the target. The received message is authenticated as a function of at least a shared key, the received publicly known constants, the security function, the received message, and the output of the security function. If the output of the security function received by the target is the same as the output generated as a function of at least the received message, the received publicly known constants, the security function, and the shared key, neither the message nor the constants have been altered.

摘要翻译： 本发明提供用于认证消息。 对消息执行安全功能。 该消息被发送到目标。 安全功能的输出被发送到目标。 至少有一个公认的常数被发送到目标。 接收到的消息被认证为至少共享密钥，接收的公知常数，安全功能，接收到的消息和安全功能的输出的功能。 如果目标接收到的安全功能的输出与至少作为接收到的消息的函数产生的输出相同，则所接收的公知常数，安全功能和共享密钥，消息和常数都不具有 被改变了

公开(公告)号：US06996233B2

公开(公告)日：2006-02-07

申请号：US10464891

申请日：2003-06-19

申请人： Daniel Alan Brokenshire ,  David Craft ,  Harm Peter Hofstee ,  Mohammad Peyravian

发明人： Daniel Alan Brokenshire ,  David Craft ,  Harm Peter Hofstee ,  Mohammad Peyravian

IPC分类号： H04L9/00 ,  H04K1/00

CPC分类号： H04L9/0618 ,  H04L2209/08 ,  H04L2209/12

摘要： A method and system for encrypting and verifying the integrity of a message using a three-phase encryption process is provided. A source having a secret master key that is shared with a target receives the message and generates a random number. The source then generates: a first set of intermediate values from the message and the random number; a second set of intermediate values from the first set of values; and a cipher text from the second set of values. At the three phases, the values are generated using the encryption function of a block cipher encryption/decryption algorithm. The random number and the cipher text are transmitted to the target, which decrypts the cipher text by reversing the encryption process. The target verifies the integrity of the message by comparing the received random number with the random number extracted from the decrypted cipher text.

摘要翻译： 提供了使用三相加密处理来加密和验证消息的完整性的方法和系统。 具有与目标共享的秘密主密钥的源接收消息并生成随机数。 然后，源产生：来自消息和随机数的第一组中间值; 来自第一组值的第二组中间值; 和来自第二组值的密文。 在三个阶段，使用块密码加密/解密算法的加密功能生成这些值。 随机数和密文被发送到目标，通过反转加密过程来解密密文。 目标通过将接收到的随机数与从解密的密文提取的随机数进行比较来验证消息的完整性。

公开(公告)号：US06865631B2

公开(公告)日：2005-03-08

申请号：US09736582

申请日：2000-12-14

申请人： Harm Peter Hofstee ,  Ravi Nair

发明人： Harm Peter Hofstee ,  Ravi Nair

IPC分类号： G06F13/24 ,  G06F13/22 ,  G06F13/28

CPC分类号： G06F13/24

摘要： A method and system for executing one or more remote procedure calls. In one embodiment, a method comprises the step of a processing unit issuing a plurality of commands to a corresponding DMA controller. One or more commands of the plurality of commands issued by the processing unit are to copy attached processing unit instructions associated with one or more Attached Processing Unit's (APU's) and data associated with the attached processing unit instructions from the shared memory to one or more APU's. The attached processing unit instructions may include instructions that enable the associated one or more APU's to perform one or more particular operations on the data. The method further comprises the DMA controller issuing an indication to the one or more APU's to perform the one or more operations on the data associated with the attached processing unit instructions. Instead of having the particular APU that completed its operation notify the corresponding processing unit of its completion of the operation, the DMA controller polls a status line of each of the one or more attached processing units to determine if any of the one or more attached processing units completed its operation. The DMA controller then copies the results of the operations after each of the one or more attached processing units completes its operation.

摘要翻译： 一种用于执行一个或多个远程过程调用的方法和系统。 在一个实施例中，一种方法包括处理单元向相应的DMA控制器发出多个命令的步骤。 由处理单元发出的多个命令的一个或多个命令是将与一个或多个附属处理单元（APU）相关联的附加处理单元指令和与附加处理单元指令相关联的附加处理单元指令从共享存储器复制到一个或多个APU 。 附加的处理单元指令可以包括使得相关联的一个或多个APU能够对数据执行一个或多个特定操作的指令。 该方法还包括DMA控制器向一个或多个APU发出指示以对与所附加的处理单元指令相关联的数据执行一个或多个操作。 DMA控制器不是使完成其操作的特定APU通知对应的处理单元完成操作，而是DMA控制器轮询一个或多个附加的处理单元中的每一个的状态行，以确定是否有一个或多个附加处理 单位完成运作。 然后，DMA控制器在每个一个或多个附加处理单元完成其操作之后复制操作的结果。

公开(公告)号：US06826110B2

公开(公告)日：2004-11-30

申请号：US10273567

申请日：2002-10-17

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Shoji Onishi ,  Osamu Takahashi

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Shoji Onishi ,  Osamu Takahashi

IPC分类号： G11C800

CPC分类号： G11C8/16

摘要： An improved cell circuit for data readout with reduced number of read wordlines is provided in a memory block of a multiport memory array. The number of read wordlines is significantly reduced by using a decoder between the read wordlines and a multiplexer in the cell circuit. The memory block has a plurality of address inputs and stores a plurality of write data signals. In the cell circuit, the decoder receives as decoder inputs a subset of the address inputs and outputs a plurality of select signals. The multiplexer is coupled to the decoder to receive the select signals and select one of the write data signals based on the select signals. Additionally, the read wordlines are coupled to the decoder for carrying the subset of the address inputs to the decoder.

摘要翻译： 在多端口存储器阵列的存储器块中提供用于具有减少读取字线数量的数据读出的改进的单元电路。 通过在读取的字线和单元电路中的多路复用器之间使用解码器来显着减少读取字线的数量。 存储块具有多个地址输入并存储多个写入数据信号。 在单元电路中，解码器接收地址输入的子集作为解码器输入并输出多个选择信号。 复用器耦合到解码器以接收选择信号，并且基于选择信号选择写入数据信号之一。 此外，读取的字线被耦合到解码器，用于将地址输入的子集携带到解码器。

公开(公告)号：US06751749B2

公开(公告)日：2004-06-15

申请号：US09791143

申请日：2001-02-22

申请人： Harm Peter Hofstee ,  Ravi Nair

发明人： Harm Peter Hofstee ,  Ravi Nair

IPC分类号： G06F1116

CPC分类号： G06F11/1407 ,  G06F9/30116 ,  G06F9/30134 ,  G06F9/3851 ,  G06F9/3863 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/1683 ,  G06F11/1691 ,  G06F2201/83

摘要： According to one embodiment, a multiprocessing system includes a first processor, a second processor, and compare logic. The first processor is operable to compute first results responsive to instructions, the second processor is operable to compute second results responsive to the instructions, and the compare logic is operable to check at checkpoints for matching of the results. Each of the processors has a first register for storing one of the processor's results, and the register has a stack of shadow registers. The processor is operable to shift a current one of the processor's results from the first register into the top shadow register, so that an earlier one of the processor's results can be restored from one of the shadow registers to the first register responsive to the compare logic determining that the first and second results mismatch. It is advantageous that the shadow register stack is closely coupled to its corresponding register, which provides for fast restoration of results. In a further aspect of an embodiment, each processor has a signature generator and a signature storage unit. The signature generator and storage units are operable to cooperatively compute a cumulative signature for a sequence of the processor's results, and the processor is operable to store the cumulative signature in the signature storage unit pending the match or mismatch determination by the compare logic. The checking for matching of the results includes the compare logic comparing the cumulative signatures of each respective processor. It is faster, and therefore advantageous, to check respective cumulative signatures at intervals rather than to check each individual result.

摘要翻译： 根据一个实施例，多处理系统包括第一处理器，第二处理器和比较逻辑。 第一处理器可操作以响应于指令来计算第一结果，第二处理器可操作以响应于指令计算第二结果，并且比较逻辑可操作以在检查点处检查结果的匹配。 每个处理器具有用于存储处理器结果之一的第一寄存器，并且寄存器具有一叠影子寄存器。 处理器可操作以将处理器的结果中的当前一个从第一寄存器移位到顶部影子寄存器，使得响应于比较逻辑，处理器结果中的较早的一个可以从一个影子寄存器恢复到第一个寄存器 确定第一和第二个结果不匹配。 影子寄存器堆栈与其对应的寄存器紧密耦合是有利的，其提供快速恢复结果。 在实施例的另一方面，每个处理器具有签名生成器和签名存储单元。 签名生成器和存储单元可操作用于协调地计算处理器结果的序列的累积签名，并且处理器可操作地将累积签名存储在签名存储单元中，等待比较逻辑的匹配或不匹配确定。 检查结果的匹配包括比较每个相应处理器的累积签名的比较逻辑。 检查相应的累积签名是更快，因此是有利的，而不是检查每个单独的结果。

公开(公告)号：US06629235B1

公开(公告)日：2003-09-30

申请号：US09564943

申请日：2000-05-05

申请人： Brian King Flachs ,  Harm Peter Hofstee ,  Kevin John Nowka

发明人： Brian King Flachs ,  Harm Peter Hofstee ,  Kevin John Nowka

IPC分类号： G06F944

CPC分类号： G06F9/30094 ,  G06F9/3842

摘要： A condition code register architecture for supporting multiple execution units is disclosed. A master execution unit is coupled a master condition code register such that condition codes generated by the master execution unit are stored in the master condition code register. A non-master execution unit is coupled to a shadow condition code register such that condition codes generated by the non-master execution unit are stored in the shadow condition code register. A tag unit coupled to the master execution unit and the non-master execution unit such that an entry within the master condition code register can be read only when a corresponding entry within the tag unit is referenced to the master execution unit or the master condition code register.

摘要翻译： 公开了一种用于支持多个执行单元的条件码寄存器架构。 主执行单元耦合主状态代码寄存器，使得由主执行单元生成的条件代码被存储在主状态代码寄存器中。 非主执行单元耦合到阴影条件代码寄存器，使得由非主执行单元生成的条件代码被存储在阴影条件代码寄存器中。 耦合到主执行单元和非主执行单元的标签单元，使得只有在标签单元内的相应条目被引用到主执行单元或主条件代码时才能读取主条件代码寄存器内的条目 寄存器。

公开(公告)号：US06507115B2

公开(公告)日：2003-01-14

申请号：US09736584

申请日：2000-12-14

申请人： Harm Peter Hofstee ,  Robert Kevin Montoye ,  Edmund Juris Sprogis

发明人： Harm Peter Hofstee ,  Robert Kevin Montoye ,  Edmund Juris Sprogis

IPC分类号： H01L2348

CPC分类号： H01L23/4334 ,  H01L23/3677 ,  H01L23/49816 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A multi-chip module is disclosed in which a first die connects to a second set of die via a set of C4 connections within a single package. Low resistivity signal posts are provided within the lateral separation between adjacent die in the second set of die. These signal posts are connectable to externally supplied power signals. The power signals provided to the signals posts are routed to circuits within the second set of die over relatively short metallization interconnects. The signal posts may be connected to thermally conductive via elements and the package may include heat spreaders on upper and lower package surfaces. The first die may comprise a DRAM while the second set of die comprise portions of a general purpose microprocessor. The power signals provided to the second set of die may be connected to a capacitor terminal in the first die to provide power signal decoupling.

公开(公告)号：US06430672B1

公开(公告)日：2002-08-06

申请号：US09617829

申请日：2000-07-17

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Osamu Takahashi ,  Jan van Lunteren

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Osamu Takahashi ,  Jan van Lunteren

IPC分类号： G06F1210

CPC分类号： G06F12/0607 ,  G06F12/0292

摘要： A method for performing address mapping for a memory within a computer system is disclosed. The memory is organized in multiple of memory banks, and each memory bank is identified by a respective bank number. A block address portion of a physical address is translated to a corresponding bank number and an associated internal bank address. The bank number is formed by concatenating an output from a first lookup table and an output from a second lookup table. The output from the first lookup table is obtained by a first and a second segments of the block address portion, while the output from the second lookup table is obtained by a third and a fourth segments of the block address portion. Data stored in a specific location within the memory banks can be accessed by the bank number and the associated internal bank address.

摘要翻译： 公开了一种用于对计算机系统内的存储器执行地址映射的方法。 存储器组织在多个存储体中，并且每个存储体由相应的存储体号标识。 物理地址的块地址部分被转换为对应的银行号码和相关联的内部银行地址。 通过连接来自第一查找表的输出和来自第二查找表的输出来形成库号。 来自第一查找表的输出由块地址部分的第一和第二段获得，而来自第二查找表的输出由块地址部分的第三和第四段获得。 可以通过银行号码和相关联的内部银行地址访问存储在存储体中的特定位置的数据。