公开(公告)号：US20140119141A1

公开(公告)日：2014-05-01

申请号：US13660768

申请日：2012-10-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Robert Tamlyn ,  Debra M. Bell ,  Michael Roth ,  Eric A. Becker ,  Tyrel Z. Jensen

IPC: G11C8/18

CPC classification number: G11C29/028 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222 ,  G11C29/022 ,  G11C29/023 ,  G11C2207/105

Abstract: Apparatuses and methods for capturing data in a memory are disclosed herein. An apparatus may include a command path and a data capture logic. The command path may be configured to receive a command signal and to delay the command signal with a delay based, at least in part, on a plurality of propagation delays. The data capture logic may be coupled to the command path and configured to receive the delayed command signal and a data strobe signal. The data capture logic may further be configured to capture data according to the data strobe signal responsive, at least in part, to receipt of the delayed command signal.

Abstract translation: 本文公开了用于在存储器中捕获数据的装置和方法。 装置可以包括命令路径和数据捕获逻辑。 命令路径可以被配置为接收命令信号并且至少部分地基于多个传播延迟延迟基于延迟的命令信号。 数据捕获逻辑可以耦合到命令路径并且被配置为接收延迟的命令信号和数据选通信号。 数据采集​​逻辑还可以被配置为至少部分地响应于接收延迟的命令信号而根据数据选通信号捕获数据。

公开(公告)号：US11755412B2

公开(公告)日：2023-09-12

申请号：US17539714

申请日：2021-12-01

Applicant: Micron Technology, Inc.

Inventor： Todd M. Buerkle ,  Debra M. Bell ,  Joshua E. Alzheimer

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/38

CPC classification number: G06F11/1076 ,  G06F11/1012 ,  G06F11/1052 ,  G11C29/38

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may directly access a portion of memory array that is otherwise reserved for ECC functionality of a memory device. The memory array may correspond to a set of memory addresses, where each memory address of the set corresponds to a first portion of the memory array (e.g., user data plane) and to a second portion of the memory array (e.g., ECC plane). The second portion may be configured to store ECC data or second user data or metadata based on whether the ECC functionality is enabled or disabled. The memory device may determine a command directed to the memory address of the set is configured to access the first portion or the second portion based on a status of a pin associated with the command.

公开(公告)号：US11735247B2

公开(公告)日：2023-08-22

申请号：US17672537

申请日：2022-02-15

Applicant: Micron Technology, Inc.

Inventor： Gitanjali T. Ghosh ,  Debra M. Bell ,  Arunmozhi R. Subramaniam ,  Roya Baghi ,  Deepika Thumsi Umesh ,  Sue-Fern Ng

IPC: G11C11/408 ,  G11C11/4099 ,  G11C11/4076 ,  G11C11/4074

CPC classification number: G11C11/4085 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4099

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to monitor degradations in word line characteristics. The memory device may generate a reference signal in response to an access command directed to a memory array including a plurality of word lines, in some embodiments. The memory array may include a victim word line configured to accumulate adverse effects of executing multiple access commands at the word lines of the memory array. When the degradation in the word line characteristics causes reliability issues (e.g., corrupted data), the memory array is deemed unreliable, and may be blocked from memory operations. The memory device may compare the reference signal and a signal from the victim word line to determine whether preventive measures may be appropriate to avoid (or mitigate) such reliability issues.

公开(公告)号：US20230186619A1

公开(公告)日：2023-06-15

申请号：US18164018

申请日：2023-02-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Di Wu ,  Anthony D. Veches ,  James S. Rehmeyer ,  Debra M. Bell ,  Libo Wang

IPC: G06V10/94 ,  G06N5/047 ,  G06N20/00 ,  G06F18/22 ,  G06V10/75

CPC classification number: G06V10/94 ,  G06N5/047 ,  G06N20/00 ,  G06F18/22 ,  G06V10/75

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods for performing operations associated with machine learning. Machine learning operations may include processing a data set, training a machine learning algorithm, and applying a trained algorithm to a data set. Some of the machine learning operations, such as pattern matching operations, may be performed within a memory device.

公开(公告)号：US11663124B2

公开(公告)日：2023-05-30

申请号：US16800356

申请日：2020-02-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： James S. Rehmeyer ,  Libo Wang ,  Anthony D. Veches ,  Debra M. Bell ,  Di Wu

IPC: G06F11/00 ,  G06F12/06 ,  G06F16/2455 ,  G06F11/10

CPC classification number: G06F12/0646 ,  G06F11/1068 ,  G06F16/24558 ,  G06F2212/70

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods, and memories that are capable of performing pattern matching operations within a memory device. The pattern matching operations may be performed on data stored within the memory based on a pattern stored in a register. The result of the pattern matching operation may be provided by the memory. The data may be retrieved from a memory array for the pattern matching operation by a read operation, a refresh operation, an error correction operation, and/or a pattern matching operation. The data may be retrieved from incoming data input lines instead of or in addition to the memory array. How the data is stored or retrieved for pattern matching operations may be controlled by a memory controller.

公开(公告)号：US11581031B2

公开(公告)日：2023-02-14

申请号：US17338191

申请日：2021-06-03

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C16/04 ,  G11C11/406 ,  G11C29/00 ,  G11C11/409 ,  G11C11/4074

Abstract: Memory with partial bank refresh is disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a memory bank with a plurality of memory cells arranged in a plurality of memory rows and (ii) circuitry. In some embodiments, the circuitry is configured to disable at least one memory row of the memory bank from receiving refresh commands such that memory cells of the at least one memory row are not refreshed during refresh operations of the memory device. In some embodiments, the memory controller is configured to track memory rows that include utilized memory cells and/or to write data to the memory rows in accordance with a programming sequence of the memory device.

公开(公告)号：US20220335993A1

公开(公告)日：2022-10-20

申请号：US17811153

申请日：2022-07-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Di Wu ,  Debra M. Bell ,  Anthony D. Veches ,  James S. Rehmeyer ,  Libo Wang

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/10 ,  G11C11/4096 ,  G11C11/4076

Abstract: Tracking circuitry may be used to determine if commands and/or command sequences include illegal commands and/or illegal command sequences. If the commands and/or command sequences include illegal commands and/or illegal command sequences, the tracking circuitry may activate signals that prevent execution of the commands and/or notice of the detected illegal commands and/or command sequences.

公开(公告)号：US11442940B2

公开(公告)日：2022-09-13

申请号：US16807692

申请日：2020-03-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Debra M. Bell ,  Libo Wang ,  Di Wu ,  James S. Rehmeyer ,  Anthony D. Veches

IPC: G06F16/2455 ,  G11C11/407 ,  G11C11/4096 ,  G11C11/54 ,  G11C7/10

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods, and memories that are capable of performing pattern matching operations within a memory device. The pattern matching operations may be performed on data stored within the memory based on a pattern stored in a register. The result of the pattern matching operation may be provided by the memory. The data on which the pattern matching operation is performed may not be output from the memory during the pattern matching operation.

公开(公告)号：US11409674B2

公开(公告)日：2022-08-09

申请号：US17062484

申请日：2020-10-02

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Vaughn N. Johnson ,  Kyle Alexander ,  Gary L. Howe ,  Brian T. Pecha ,  Miles S. Wiscombe

IPC: G06F13/16 ,  G11C11/406 ,  G11C11/4096

Abstract: Memory devices and systems with improved command/address bus utilization are disclosed herein. In one embodiment, a memory device comprises a plurality of external command/address terminals and a command decoder. The plurality of external command/address terminals are configured to receive a command as a corresponding plurality of command/address bits. A first set of the command/address bits indicate a read or write operation. A second set of the command/address bits indicate whether to execute a refresh operation. The memory device is configured to, in response to the first set of command/address bits, execute the read or write operation on a portion of a memory array. The memory device is further configured to, in response to the second set of command/address bits, execute the refresh operation to refresh at least one memory bank of the memory array when the second set of command/address bits indicate that the refresh operation should be executed.

公开(公告)号：US11361808B2

公开(公告)日：2022-06-14

申请号：US16160801

申请日：2018-10-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Debra M. Bell ,  Jeff A. McClain ,  Brian P. Callaway

IPC: G11C11/406 ,  G11C7/10

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.