公开(公告)号：US07005376B2

公开(公告)日：2006-02-28

申请号：US10615086

申请日：2003-07-07

申请人： Robert J. Chiu ,  Jeffrey P. Patton ,  Paul R. Besser ,  Minh Van Ngo

发明人： Robert J. Chiu ,  Jeffrey P. Patton ,  Paul R. Besser ,  Minh Van Ngo

IPC分类号： H01L21/00

CPC分类号： H01L21/28518

摘要： A method of forming and a structure of an integrated circuit are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform silicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.

摘要翻译： 提供一种集成电路的形成方法和结构。 在半导体衬底上形成栅极电介质，并且在半导体衬底上的栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结上形成超均匀的硅化物，并且在半导体衬底上沉积电介质层。 然后在电介质层中形成与超均匀硅化物的接触。

公开(公告)号：US06979642B1

公开(公告)日：2005-12-27

申请号：US10628733

申请日：2003-07-28

申请人： Matthew S. Buynoski ,  Connie Pin-Chin Wang ,  Paul R. Besser ,  Minh Q. Tran

发明人： Matthew S. Buynoski ,  Connie Pin-Chin Wang ,  Paul R. Besser ,  Minh Q. Tran

IPC分类号： H01L21/283 ,  H01L21/288 ,  H01L21/321 ,  H01L21/768

CPC分类号： H01L21/2885 ,  H01L21/321 ,  H01L21/76877

摘要： A method of forming a conductive structure such as a copper conductive structure, line, or via is optimized for large grain growth and distribution of alloy elements. The alloy elements can reduce electromigration problems associated with the conductive structure. The conductive structure is self-annealed or first annealed in a low temperature process over a longer period of time. Another anneal is utilized to distribute alloy elements.

摘要翻译： 形成诸如铜导电结构，管线或通孔的导电结构的方法被优化用于合金元件的大晶粒生长和分布。 合金元素可以减少与导电结构相关的电迁移问题。 导电结构在较长时间内在低温过程中自退火或首先退火。 利用另一退火来分配合金元素。

公开(公告)号：US06861349B1

公开(公告)日：2005-03-01

申请号：US10145944

申请日：2002-05-15

申请人： Sergey D. Lopatin ,  Paul R. Besser ,  Matthew S. Buynoski ,  Pin-Chin Connie Wang

发明人： Sergey D. Lopatin ,  Paul R. Besser ,  Matthew S. Buynoski ,  Pin-Chin Connie Wang

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76859 ,  H01L21/76873 ,  H01L21/76874

摘要： A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into an interfacial layer over the barrier material layer, depositing an alloy layer over the interfacial layer. The implanted first alloy element is reactive with the barrier material layer to increase resistance to copper diffusion.

摘要翻译： 一种制造集成电路的方法可以包括沿着侧壁和形成通孔的底部形成阻挡材料层，所述通孔被配置为接收电连接第一导电层和第二导电层的通孔材料，注入第一合金 元素进入阻挡材料层上的界面层，在界面层上沉积合金层。 植入的第一合金元素与阻挡材料层反应，以增加对铜扩散的抗性。

公开(公告)号：US06835656B1

公开(公告)日：2004-12-28

申请号：US10163459

申请日：2002-06-07

申请人： Paul R. Besser ,  Minh Van Ngo

发明人： Paul R. Besser ,  Minh Van Ngo

IPC分类号： H01L2144

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/28525

摘要： A method for forming ultra-shallow junctions in a semiconductor wafer with reduced silicon consumption during salicidation supplies additional silicon during the salicidation process. After the gate and source/drain junctions are formed in a semiconductor device, high-resistivity metal silicide regions are formed on the gate and source/drain junctions. Amorphous silicon is then deposited in a layer on the high resistivity metal silicide regions by high density plasma chemical vapor deposition. The deposition of the amorphous-silicon is at an elevated temperature which causes transforming of the high resistivity metal silicide regions to low resistivity metal silicide regions on the gate and source/drain junctions. The deposited amorphous-silicon acts as a source of silicon that is employed as a diffusion species during the transformation of the high resistivity metal silicide to the low resistivity metal silicide.

摘要翻译： 用于在半衰期期间形成超浅结的方法，其中在硅化过程中硅消耗减少，在盐析过程中提供额外的硅。 在半导体器件中形成栅极和源极/漏极结之后，在栅极和源极/漏极结上形成高电阻金属硅化物区域。 然后通过高密度等离子体化学气相沉积将非晶硅沉积在高电阻率金属硅化物区域的一层中。 非晶硅的沉积处于升高的温度，这导致高电阻率金属硅化物区域转变为栅极和源极/漏极结上的低电阻率金属硅化物区域。 沉积的非晶硅在高电阻率金属硅化物向低电阻率金属硅化物的转变期间充当硅源，用作扩散物质。

公开(公告)号：US06835655B1

公开(公告)日：2004-12-28

申请号：US09994397

申请日：2001-11-26

申请人： Paul R. Besser ,  Matthew S. Buynoski ,  Sergey D. Lopatin

发明人： Paul R. Besser ,  Matthew S. Buynoski ,  Sergey D. Lopatin

IPC分类号： H01L2144

CPC分类号： H01L23/53238 ,  H01L21/76843 ,  H01L21/76859 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of implanting copper barrier material to improve electrical performance in an integrated circuit fabrication process can include providing a copper layer over an integrated circuit substrate, providing a barrier material at a bottom and sides of a via positioned over the copper layer to form a barrier material layer separating the via from the copper layer, implanting a metal species into the barrier material layer, and providing a conductive layer over the via such that the via electrically connects the conductive layer to the copper layer. The implanted metal species can make the barrier material layer more resistant to copper diffusion from the copper layer.

摘要翻译： 在集成电路制造工艺中注入铜阻挡材料以提高电性能的方法可以包括在集成电路基板上提供铜层，在位于铜层上方的通孔的底部和侧面提供阻挡材料以形成屏障 将所述通孔与所述铜层分离的材料层，将金属物质注入到所述阻挡材料层中，以及在所述通孔上方提供导电层，使得所述通孔将所述导电层电连接到所述铜层。 注入的金属物质可以使阻挡材料层更能抵抗铜层从铜层扩散。

公开(公告)号：US06811448B1

公开(公告)日：2004-11-02

申请号：US10619879

申请日：2003-07-15

申请人： Eric N. Paton ,  Paul R. Besser ,  Qi Xiang

发明人： Eric N. Paton ,  Paul R. Besser ,  Qi Xiang

IPC分类号： H01L21302

CPC分类号： H01L21/02054 ,  H01L21/02046 ,  H01L21/02052 ,  H01L21/28518 ,  H01L29/665

摘要： A fabrication system utilizes a protocol for removing native oxide from a top surface of a wafer. An exposure to a plasma, such as a plasma containing hydrogen and argon can remove the native oxide from the top surface without causing excessive germanium contamination. The protocol can use a hydrogen fluoride dip. The hydrogen fluoride dip can be used before the plasma is used. The protocol allows better silicidation in SMOS devices.

摘要翻译： 制造系统利用用于从晶片顶表面去除自然氧化物的协议。 暴露于等离子体，例如含有氢气和氩气的等离子体可从顶表面除去天然氧化物，而不会引起过量的锗污染。 该方案可以使用氟化氢浸渍。 在使用等离子体之前可以使用氟化氢浸渍。 该协议允许在SMOS器件中更好的硅化。

公开(公告)号：US06764912B1

公开(公告)日：2004-07-20

申请号：US09919943

申请日：2001-08-02

申请人： John Clayton Foster ,  Eric N. Paton ,  Matthew S. Buynoski ,  Qi Xiang ,  Paul R. Besser ,  Paul L. King

发明人： John Clayton Foster ,  Eric N. Paton ,  Matthew S. Buynoski ,  Qi Xiang ,  Paul R. Besser ,  Paul L. King

IPC分类号： H01L21336

CPC分类号： H01L21/28194 ,  H01L29/51 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656

摘要： The formation of metal silicides in silicon nitride spacers on a gate electrode causes bridging between a gate electrode and the source and drain regions of a semiconductor device. The bridging is prevented by forming a thin layer of silicon oxide on the silicon nitride spacers prior to forming the metal silicide layers on the device.

摘要翻译： 栅电极上的氮化硅间隔物中的金属硅化物的形成导致栅电极与半导体器件的源区和漏区之间的桥接。 通过在器件上形成金属硅化物层之前在氮化硅间隔物上形成氧化硅薄层来防止桥接。

公开(公告)号：US06703308B1

公开(公告)日：2004-03-09

申请号：US09994400

申请日：2001-11-26

申请人： Paul R. Besser ,  Matthew S. Buynoski ,  Sergey D. Lopatin ,  Alline F. Myers ,  Phin-Chin Connie Wang

发明人： Paul R. Besser ,  Matthew S. Buynoski ,  Sergey D. Lopatin ,  Alline F. Myers ,  Phin-Chin Connie Wang

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/76849 ,  H01L21/76859 ,  H01L21/76867

摘要： A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into the barrier material layer, and implanting a second alloy element after deposition of the via material. The implanted first alloy element makes the barrier material layer more resistant to copper diffusion. The implanted second alloy element diffuses to a top interface of the via material and reduces bulk diffusion from the via material.

摘要翻译： 一种制造集成电路的方法可以包括沿着侧壁和形成通孔的底部形成阻挡材料层，所述通孔被配置为接收电连接第一导电层和第二导电层的通孔材料，注入第一合金 元件进入阻挡材料层，以及在沉积通孔材料之后注入第二合金元件。 植入的第一合金元素使得阻挡材料层更能抵抗铜扩散。 植入的第二合金元件扩散到通孔材料的顶部界面并且减小从通孔材料的体积扩散。

公开(公告)号：US06633085B1

公开(公告)日：2003-10-14

申请号：US09884100

申请日：2001-06-20

申请人： Paul R. Besser ,  Larry Zhao ,  Donggang David Wu

发明人： Paul R. Besser ,  Larry Zhao ,  Donggang David Wu

IPC分类号： H01L2348

CPC分类号： H01L21/76814 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/76886 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal interconnect structure and method of making the same implants ions of an alloy elements into a copper line through a via. Then ion implantation of the alloy elements in the copper line through the via provides improved electromigration properties at the copper line at a critical electromigration failure site, without attempting to provide alloy elements throughout the entire copper line.

摘要翻译： 一种金属互连结构和方法，通过通孔将合金元素的离子注入铜线。 然后通过通孔离子注入铜线中的合金元素，在临界电迁移破坏部位的铜线处提供了改善的电迁移特性，而不试图在整个铜线上提供合金元素。

公开(公告)号：US06605513B2

公开(公告)日：2003-08-12

申请号：US09729699

申请日：2000-12-06

申请人： Eric N. Paton ,  Ercan Adem ,  Jacques J. Bertrand ,  Paul R. Besser ,  Matthew S. Buynoski ,  John Clayton Foster ,  Paul L. King ,  George Jonathan Kluth ,  Minh Van Ngo ,  Christy Mei-Chu Woo

发明人： Eric N. Paton ,  Ercan Adem ,  Jacques J. Bertrand ,  Paul R. Besser ,  Matthew S. Buynoski ,  John Clayton Foster ,  Paul L. King ,  George Jonathan Kluth ,  Minh Van Ngo ,  Christy Mei-Chu Woo

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/28061 ,  H01L21/28518 ,  H01L29/4933

摘要： A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy is reacted with a silicon material to form at least one high resistance nickel silicide region. Unreacted nickel is removed. A dielectric layer is then deposited over a high resistance nickel silicide regions. In a second temperature treatment, the at least one high resistance nickel silicide region and dielectric layer are reacted at a prescribed temperature to form at least one low resistance silicide region and process the dielectric layer. Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel between silicide regions is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions and the dielectric layer are conveniently combined into a single temperature treatment.

摘要翻译： 自对准硅化物工艺，可以适应低热预算，并在受控反应中形成小尺寸的硅化物区域。 在第一温度处理中，镍金属或镍合金与硅材料反应以形成至少一个高电阻镍硅化物区域。 去除未反应的镍。 然后将电介质层沉积在高电阻镍硅化物区域上。 在第二温度处理中，至少一个高电阻镍硅化物区域和电介质层在规定温度下反应以形成至少一个低电阻硅化物区域并处理介电层。 通过控制硅化物生长的两步法避免区域之间的桥接，并且在第一温度处理之后去除硅化物区域之间的未反应的镍。 将高电阻镍硅化物区域和电介质层的处理方便地组合成单温度处理。