公开(公告)号：US20170062439A1

公开(公告)日：2017-03-02

申请号：US15347530

申请日：2016-11-09

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Ritu Chaba ,  Ping Liu ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: H01L27/11 ,  H01L23/528 ,  G11C11/419 ,  H01L21/768 ,  H01L21/3213 ,  H01L27/02 ,  H01L23/522

CPC classification number: H01L27/1104 ,  G11C8/14 ,  G11C8/16 ,  G11C11/418 ,  G11C11/419 ,  H01L21/3213 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11

Abstract: An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.

Abstract translation: 一种装置包括耦合到位单元的第一金属层。 该装置还包括第三金属层，其包括耦合到位单元的写入字线。 该装置还包括在第一金属层和第三金属层之间的第二金属层。 第二金属层包括耦合到位单元的两个读字线。

公开(公告)号：US09564361B2

公开(公告)日：2017-02-07

申请号：US14026893

申请日：2013-09-13

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang ,  John Jianhong Zhu

IPC: H01L21/768 ,  G06F17/50 ,  H01L23/522 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/76816 ,  G06F17/5068 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/66 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first sidewall structure to expose a first portion of a first hardmask layer. The method also includes etching the first portion of the first hardmask layer to expose a second portion of a dielectric material. The method also includes etching the second portion of the dielectric material to form a first trench. The method also includes forming a first metal structure within the first trench.

Abstract translation: 在特定实施例中，一种方法包括形成与第一侧壁结构相邻并与半导体器件的心轴相邻的第二硬掩模层。 心轴的顶部在形成第二硬掩模层之前被暴露。 该方法还包括去除第一侧壁结构以暴露第一硬掩模层的第一部分。 该方法还包括蚀刻第一硬掩模层的第一部分以暴露电介质材料的第二部分。 该方法还包括蚀刻介电材料的第二部分以形成第一沟槽。 该方法还包括在第一沟槽内形成第一金属结构。

公开(公告)号：US09542518B2

公开(公告)日：2017-01-10

申请号：US14656426

申请日：2015-03-12

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Kern Rim ,  Choh Fei Yeap

IPC: G06F17/50 ,  G06F15/76

CPC classification number: G06F17/5045 ,  G06F15/76

Abstract: A method for designing a system-on-chip (SOC) for a wireless device includes receiving, at a design processor, first usage conditions for a first module of the SOC and second usage conditions for a second module of the SOC. The method further includes determining design parameters for the SOC. The design parameters are determined based on the first usage conditions and the second usage conditions.

Abstract translation: 一种用于设计用于无线设备的片上系统（SOC）的方法包括：在设计处理器处接收所述SOC的第一模块的第一使用条件和所述SOC的第二模块的第二使用条件。 该方法还包括确定SOC的设计参数。 基于第一使用条件和第二使用条件来确定设计参数。

公开(公告)号：US09502283B2

公开(公告)日：2016-11-22

申请号：US14627653

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Da Yang ,  Choh Fei Yeap

IPC: H01L21/768 ,  G06F17/50 ,  H01L21/311 ,  H01L23/535 ,  G03F1/00 ,  G03F7/20

CPC classification number: H01L21/76802 ,  G03F1/14 ,  G03F7/203 ,  G03F7/70425 ,  G03F7/70433 ,  G03F7/7045 ,  G03F7/70466 ,  G06F17/5077 ,  H01L21/31116 ,  H01L23/535

Abstract: Electron-beam (e-beam) based semiconductor device features are disclosed. In a particular aspect, a method includes performing a first lithography process to fabricate a first set of cut pattern features on a semiconductor device. A distance of each feature of the first set of cut pattern features from the feature to an active area is greater than or equal to a threshold distance. The method further includes performing an electron-beam (e-beam) process to fabricate a second cut pattern feature on the semiconductor device. A second distance of the second cut pattern feature from the second cut pattern feature to the active area is less than or equal to the threshold distance.

Abstract translation: 公开了基于电子束（e-beam）的半导体器件特征。 在特定方面，一种方法包括执行第一光刻工艺以在半导体器件上制造第一组切割图案特征。 从特征到有效区域的第一组切割图案特征的每个特征的距离大于或等于阈值距离。 该方法还包括执行电子束（e-beam）工艺以在半导体器件上制造第二切割图案特征。 第二切割图案特征从第二切割图案特征到有效区域的第二距离小于或等于阈值距离。

公开(公告)号：US20160247554A1

公开(公告)日：2016-08-25

申请号：US14631603

申请日：2015-02-25

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Zhongze Wang ,  Xiaonan Chen ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/20 ,  G11C11/417 ,  G11C29/021 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/0407 ,  G11C2029/0409 ,  G11C2029/5002

Abstract: An apparatus includes a static random-access memory and circuitry configured to initiate a corrective action associated with the static random-access memory. The corrective action may be initiated based on a number of static random-access memory cells that have a particular state responsive to a power-up of the static random-access memory.

Abstract translation: 一种装置包括静态随机存取存储器和被配置为发起与静态随机存取存储器相关联的校正动作的电路。 可以基于具有响应于静态随机存取存储器的加电的特定状态的多个静态随机存取存储器单元来启动校正动作。

公开(公告)号：US09424909B1

公开(公告)日：2016-08-23

申请号：US14659937

申请日：2015-03-17

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Ping Liu ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: G11C11/00 ,  G11C11/417 ,  G06F17/50 ,  G11C11/412

CPC classification number: G11C11/417 ,  G06F17/5068 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/54 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: Aspects disclosed include static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation. In one aspect, a method of designing SRAM arrays with multiple modes operation is provided. The method includes determining performance characteristics associated with each mode of operation. SRAM bit cells configured to operate in each mode of operation are provided to the SRAM array. SRAM bit cells are biased to operate in a mode of operation using dynamic adaptive assist techniques, wherein the SRAM bit cells achieve a substantially constant operational yield across the modes. The SRAM bit cells have a corresponding type, wherein the number of SRAM bit cell types in the method is less than the number of modes of operation. Thus, each SRAM array may achieve a particular mode of operation without requiring a separate SRAM bit cell type for each mode, thereby reducing costs.

Abstract translation: 所公开的方面包括在多种操作模式下具有基本恒定的操作成品率的静态随机存取存储器（SRAM）阵列。 在一个方面，提供了一种设计具有多种模式操作的SRAM阵列的方法。 该方法包括确定与每个操作模式相关联的性能特征。 配置为在每个操作模式下操作的SRAM位单元被提供给SRAM阵列。 SRAM位单元被偏置以在使用动态自适应辅助技术的操作模式下操作，其中SRAM位单元在整个模式下实现基本上恒定的运行产量。 SRAM位单元具有相应的类型，其中方法中的SRAM位单元类型的数量小于操作模式的数量。 因此，每个SRAM阵列可以实现特定的操作模式，而不需要用于每个模式的单独的SRAM位单元类型，从而降低成本。

公开(公告)号：US09379058B2

公开(公告)日：2016-06-28

申请号：US14274184

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Zhongze Wang ,  Ohsang Kwon ,  Kern Rim ,  John Jianhong Zhu ,  Xiangdong Chen ,  Foua Vang ,  Raymond George Stephany ,  Choh Fei Yeap

IPC: H01L29/423 ,  H01L29/417 ,  H01L23/528 ,  H01L23/522 ,  H01L27/088 ,  H01L21/768 ,  H01L27/118

CPC classification number: H01L23/5283 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/088 ,  H01L29/41775 ,  H01L29/42312 ,  H01L2027/11866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically coupled to the first active contact, including a first isolation layer on sidewalls electrically isolating the first stacked contact from the gate. The device also includes a first via electrically coupled to the gate and landing on the first stacked contact. The first via electrically couples the first stacked contact and the first active contact to the gate to ground the gate.

Abstract translation: 半导体器件包括栅极和邻近栅极的第一有源触点。 这种器件还包括电耦合到第一有源触点的第一堆叠触点，包括在侧壁上电隔离第一堆叠触头与栅极的第一隔离层。 该装置还包括电连接到门的第一通孔和第一堆叠接触件上的着陆。 第一通孔将第一堆叠触点和第一有源触点电耦合到栅极以将栅极接地。

公开(公告)号：US20160163714A1

公开(公告)日：2016-06-09

申请号：US14559258

申请日：2014-12-03

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Kern Rim ,  Choh Fei Yeap

IPC: H01L27/11 ,  G11C11/412 ,  G11C5/06 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L27/11 ,  G11C5/063 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  H01L21/768 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells are disclosed. In one aspect, an SRAM bit cell is disclosed employing write wordline in second metal layer, first read wordline in third metal layer, and second read wordline in fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have wider widths, which decrease wordline resistance, decrease access time, and increase performance of SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks inside and outside of a boundary edge of the SRAM bit cell. Landing pads corresponding to the write wordline are placed on corresponding tracks within the boundary edge of the SRAM bit cell.

Abstract translation: 公开了在SRAM位单元的边界边缘分割的具有字线着色焊盘的静态随机存取存储器（SRAM）位单元。 一方面，公开了在第二金属层中采用写入字线，第三金属层中的第一读取字线和第四金属层中的第二读取字线的SRAM位单元。 在单独的金属层中使用字线允许字线具有更宽的宽度，这降低了字线电阻，减少了访问时间，并且提高了SRAM位单元的性能。 为了在单独的金属层中采用字线，采用第一金属层中的多个轨道。 为了将读取字线耦合到轨道以与SRAM位单元晶体管通信，着陆焊盘设置在SRAM位单元的边界内部和外部的对应轨道上。 对应于写入字线的着陆焊盘被放置在SRAM位单元的边界边缘内的对应的轨道上。

公开(公告)号：US09349686B2

公开(公告)日：2016-05-24

申请号：US14206360

申请日：2014-03-12

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang ,  Niladri Mojumder ,  Mustafa Badaroglu

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/02167 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.

Abstract translation: 系统和方法涉及一种集成电路，其包括由具有比铜的平均自由路径更低的示例性材料形成的减小的高度M1金属线，用于集成电路的片上电路元件的局部布线，其中降低的高度 M1金属线低于由铜形成的常规M1金属线的最小允许或允许的高度。 用于形成还原高度M1金属线的示例性材料包括钨（W），钼（Mo）和钌（Ru），其中这些示例性材料还具有比铜更低的电容和更低的RC延迟，同时提供高电迁移可靠性。

公开(公告)号：US20160140275A1

公开(公告)日：2016-05-19

申请号：US14656426

申请日：2015-03-12

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Kern Rim ,  Choh Fei Yeap

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F15/76

Abstract: A method for designing a system-on-chip (SOC) for a wireless device includes receiving, at a design processor, first usage conditions for a first module of the SOC and second usage conditions for a second module of the SOC. The method further includes determining design parameters for the SOC. The design parameters are based on the first usage conditions and the second usage conditions.

Abstract translation: 一种用于设计用于无线设备的片上系统（SOC）的方法包括：在设计处理器处接收所述SOC的第一模块的第一使用条件和所述SOC的第二模块的第二使用条件。 该方法还包括确定SOC的设计参数。 设计参数基于第一使用条件和第二使用条件。