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公开(公告)号：US20200007363A1
公开(公告)日：2020-01-02
申请号：US16455479
申请日：2019-06-27
Applicant: Rambus Inc.
Inventor： Masum Hossain , Nhat Nguyen , Charles Walter Boecker
Abstract: A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.
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公开(公告)号：US20190245548A1
公开(公告)日：2019-08-08
申请号：US16272236
申请日：2019-02-11
Applicant: Rambus Inc.
Inventor： Masum Hossain , Kenneth C. Dyer , Nhat Nguyen , Shankar Tangirala
Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
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公开(公告)号：US20180152284A1
公开(公告)日：2018-05-31
申请号：US15799016
申请日：2017-10-31
Applicant: Rambus Inc.
Inventor： Masum Hossain , Nhat Nguyen , Yikui Jen Dong , Arash Zargaran-Yazd
CPC classification number: H04L7/0087 , H03K7/02 , H03L7/00 , H04L7/0025 , H04L7/0337 , H04L25/4917
Abstract: A receiver serial data streams generates a local timing reference clock from an approximate frequency reference clock by phase-aligning the local clock to transitions in the data stream. This process is commonly known as clock and data recovery (CDR). Certain transitions of the data signals are selected for use in phase-aligning the local clock, and certain transitions are ignored. Phase-error signals from multiple receivers receiving the multiple serial data streams are combined and used to make common phase adjustments to the frequency reference clock. These common adjustments track jitter that is common to the received data streams. Local adjustments that better align each respective local clock to the transitions of its respective serial data stream are made using a local phase-error signal. These local adjustments track jitter that is more unique to each of the respective serial data streams.
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公开(公告)号：US09954489B2
公开(公告)日：2018-04-24
申请号：US15632045
申请日：2017-06-23
Applicant: Rambus Inc.
Inventor： Masum Hossain , Farshid Aryanfar , Mohammad Hekmat , Reza Navid
CPC classification number: H03B19/00 , G06F1/08 , G06F1/10 , H03K3/0315 , H03K5/00006 , H03L7/099
Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
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公开(公告)号：US20180019706A1
公开(公告)日：2018-01-18
申请号：US15632045
申请日：2017-06-23
Applicant: Rambus Inc.
Inventor： Masum Hossain , Farshid Aryanfar , Mohammad Hekmat , Reza Navid
CPC classification number: H03B19/00 , G06F1/08 , G06F1/10 , H03K3/0315 , H03K5/00006 , H03L7/099
Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
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Patent Agency Ranking
公开(公告)号：US20170331483A1
公开(公告)日：2017-11-16
申请号：US15605932
申请日：2017-05-25
Applicant: Rambus Inc.
Inventor： Masum Hossain , Farshid Aryanfar
CPC classification number: H03L7/235 , H03L7/0805 , H03L7/081 , H03L7/099 , H03L7/0995 , H03L7/18 , H03L7/23
Abstract: A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.
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公开(公告)号：US20170134153A1
公开(公告)日：2017-05-11
申请号：US15339342
申请日：2016-10-31
Applicant: Rambus Inc.
Inventor： Masum Hossain , Brian Leibowitz , Jihong Ren
CPC classification number: H04L7/0016 , H03L7/1974 , H03L7/235 , H04L7/033 , H04L27/0014 , H04L27/32 , H04L2027/0016 , H04L2027/0036 , H04L2027/0053 , H04L2027/0055 , H04L2027/0067
Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
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78.发明申请Wide Range Frequency Synthesizer with Quadrature Generation and Spur Cancellation 有权宽范围频率合成器，具有正交发生和正弦消除公开(公告)号：US20150365095A1
公开(公告)日：2015-12-17
申请号：US14746618
申请日：2015-06-22
Applicant: Rambus Inc.
Inventor： Masum Hossain , Farshid Aryanfar
CPC classification number: H03L7/235 , H03L7/0805 , H03L7/081 , H03L7/099 , H03L7/0995 , H03L7/18 , H03L7/23
Abstract: A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.
Abstract translation: 频率合成器从单个振荡器产生宽范围的频率，同时实现良好的噪声性能。 级联锁相环（PLL）电路包括具有LC压控振荡器（VCO）的第一PLL电路和具有环形VCO的第二PLL电路。 从第一PLL电路到第二PLL电路的前馈路径提供用于消除相位噪声的装置和信号路径，从而减少或消除杂散和量化效应。 频率合成器可以直接产生同相和正交相输出信号。 通过相位误差检测回路来控制分频环形VCO，以减少或消除正交信号之间的相位误差。
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公开(公告)号：US09036764B1
公开(公告)日：2015-05-19
申请号：US14050202
申请日：2013-10-09
Applicant: Rambus Inc.
Inventor： Masum Hossain , Jared L. Zerbe , Myeong-Jae Park
CPC classification number: H04L7/0331 , H03L7/087 , H03L7/0891 , H03L7/091 , H04L7/0025 , H04L7/0087 , H04L7/0337 , H04L25/03146 , H04L2025/03445
Abstract: This disclosure provides a clock recovery circuit having a phase-locked loop (PLL) with two-point modulation. A binary phase-error signal controls a variable frequency oscillator's (VFO's) feedback path, while a linear phase-error signal controls the PLL outside of that feedback path. The linear phase-error signal is injected using an ultra-low latency delay path. While the binary phase-error signal sets the lock-point of the PLL, the linear phase-error path dominates at high frequencies and also helps reduce dither jitter. Other optional features include an area-efficient hybrid phase detector that generates both the binary and linear phase-error signals, use of a phase interpolator inside the PLL to further smooth dither jitter, recovered clock update filtering for specific data transitions, and support for multi-PAM signaling.
Abstract translation: 本公开提供了具有具有两点调制的锁相环（PLL）的时钟恢复电路。 二进制相位误差信号控制可变频率振荡器（VFO）的反馈路径，而线性相位误差信号控制该反馈路径外的PLL。 使用超低延迟延迟路径注入线性相位误差信号。 当二进制相位误差信号设置PLL的锁定点时，线性相位误差路径在高频下占主导地位，并且有助于减少抖动抖动。 其他可选功能包括区域有效的混合相位检测器，其产生二进制和线性相位误差信号，使用PLL内的相位内插器来进一步平滑抖动抖动，针对特定数据转换的恢复时钟更新滤波，以及支持多 -PAM信令。
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公开(公告)号：US20150091617A1
公开(公告)日：2015-04-02
申请号：US14565802
申请日：2014-12-10
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Masum Hossain
CPC classification number: H03L7/16 , H03J2200/10 , H03K3/0315 , H03K5/00006 , H03K5/13 , H03K5/14 , H03L7/06 , H03L7/0995 , H03L7/24
Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
Abstract translation: 在第一时钟频率倍增器中，具有光谱交错锁定范围的多个注入锁定振荡器（ILO）并行操作，以实现基本上比孤立的国际劳工组织的输入频率范围更宽的集体输入频率范围。 在每个输入频率变化之后，可以根据一个或多个限定条件评估国际劳工组织输出时钟，以选择其中一个ILO作为最终的时钟源。 在第二个时钟倍频器中，灵活注入速率的注入锁定振荡器锁定到超谐波，次谐波或全频率注入脉冲，在不同的注入脉冲速率之间无缝转换，以实现宽的输入频率范围。 响应于输入时钟由第一和/或第二时钟频率乘法器影响的倍频因子在飞行中确定，然后与编程的（期望的）乘法因子进行比较，以在频率乘法器的不同分频实例之间进行选择 时钟。
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