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公开(公告)号：US20130127033A1
公开(公告)日：2013-05-23
申请号：US13741879
申请日：2013-01-15
Applicant: Renesas Electronics Corporation
Inventor： Yasutaka NAKASHIBA , Kenta OGAWA
IPC: H01L23/495
CPC classification number: H01L23/5227 , H01L21/56 , H01L23/48 , H01L23/49534 , H01L23/49537 , H01L23/49575 , H01L23/544 , H01L23/645 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/85 , H01L25/0657 , H01L2223/6655 , H01L2224/04042 , H01L2224/29 , H01L2224/29139 , H01L2224/2919 , H01L2224/29298 , H01L2224/32145 , H01L2224/32245 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2224/83101 , H01L2224/83855 , H01L2224/85 , H01L2224/92147 , H01L2224/92247 , H01L2225/06562 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01014 , H01L2924/01021 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/0132 , H01L2924/0665 , H01L2924/07802 , H01L2924/181 , H01L2924/3025 , H01L2924/0635 , H01L2924/00 , H01L2924/01026 , H01L2924/00012 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929 , H01L2224/85399 , H01L2224/05599
Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.
Abstract translation: 第一半导体芯片和第二半导体芯片在第一多层互连层和第二多层互连层彼此相对的方向上彼此重叠。 当在平面图中看到时，第一电感器和第二电感器重叠。 第一半导体芯片和第二半导体芯片具有不相对的非对置区域。 第一多层互连层在非对置区域中具有第一外部连接端子，并且第二多层互连层在非对置区域中具有第二外部连接端子。
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公开(公告)号：US20130076911A1
公开(公告)日：2013-03-28
申请号：US13677877
申请日：2012-11-15
Applicant: Renesas Electronics Corporation
Inventor： Yasutaka NAKASHIBA
IPC: H04N5/33
CPC classification number: H04N5/33 , G06K9/0004 , H04N9/045
Abstract: A solid-state imaging apparatus 10 includes a solid-state imaging device 40, and a color filter 16 constituted of a first color filter 16a (first filter) and a second color filter 16b (second filter). The solid-state imaging device 40 photoelectrically converts light incident to a face S1 (first face) thereof to thereby capture an image of an object to be imaged. Arranged on the face S1 of the solid-state imaging device 40 is the first color filter 16a and second color filter 16b. The first color filter 16a is a filter that allows first wavelength band light to be selectively transmitted therethrough; the second color filter 16b is a filter that allows second wavelength band light in the longer wavelength side relative to the first wavelength band to be selectively transmitted therethrough.
Abstract translation: 固态成像装置10包括固态成像装置40和由第一滤色器16a（第一滤色器）和第二滤色器16b（第二滤色器）构成的滤色器16。 固态成像装置40对入射到其表面S1（第一面）的光进行光电转换，从而捕获待成像对象的图像。 在固态成像装置40的面S1上排列的是第一滤色器16a和第二滤色器16b。 第一滤色器16a是允许选择性地透过第一波长带光的滤光器; 第二滤色器16b是允许通过其选择性地透射相对于第一波长带的较长波长侧的第二波长带光的滤光器。
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公开(公告)号：US20240128248A1
公开(公告)日：2024-04-18
申请号：US18365455
申请日：2023-08-04
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Yasutaka NAKASHIBA , Hiroshi MIYAKI , Takayuki IGARASHI
CPC classification number: H01L25/16 , H01F27/2804 , H01F27/306 , H01L24/32 , H01F27/324 , H01L24/33 , H01L24/48 , H01L24/73 , H01L2224/32245 , H01L2224/32265 , H01L2224/3303 , H01L2224/33181 , H01L2224/48091 , H01L2224/48265 , H01L2224/73265 , H01L2924/19042 , H01L2924/19104
Abstract: A semiconductor device includes an insulating substrate and an upper inductor that is formed on the insulating substrate and is a component of a transformer that performs contactless communication between different potentials. Here, the upper inductor is configured to be applied with a first potential. The upper inductor is formed so as to be magnetically coupled to a lower inductor that is configured to be applied with a second potential different from the first potential.
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公开(公告)号：US20240047576A1
公开(公告)日：2024-02-08
申请号：US18490473
申请日：2023-10-19
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Makoto KOSHIMIZU , Yasutaka NAKASHIBA
CPC classification number: H01L29/7816 , H01L29/045 , H01L29/66681
Abstract: The source region, drain region, buried insulating film, gate insulating film, and gate electrode of the semiconductor device are formed in a main surface of a semiconductor substrate. The buried insulating film is buried in a first trench formed between the source and drain regions. The first trench has a first side surface and a first bottom surface. The first side surface faces the source region in a first direction extending from one of the source and drain regions to the other. The first bottom surface is connected to the first side surface and is along the main surface of the semiconductor substrate. A crystal plane of a first surface of the semiconductor substrate, which is the first side surface of the first trench, is (111) plane. A crystal plane of a second surface of the semiconductor substrate, which is the bottom surface of the first trench, is (100) plane.
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公开(公告)号：US20230067226A1
公开(公告)日：2023-03-02
申请号：US17847952
申请日：2022-06-23
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Naohito SUZUMURA , Hiromichi TAKAOKA , Kenichiro SONODA , Hideaki TSUCHIYA , Yasutaka NAKASHIBA
IPC: H01L23/525 , H01L23/522 , H01L27/01 , H01C7/00
Abstract: An electric fuse element has a first portion, a second portion arranged on one end of the first portion, and a third portion arranged on the other end of the first portion. A resistor element is arranged separately from the electric fuse element. A material of each of the electric fuse element and the resistor element has silicon metal or nickel chromium. The electric fuse element and the resistor element are arranged in an upper layer of the first wiring and in lower layer of the second wiring. A wiring width of the second portion and a wiring width of the third portion are larger than a wiring width of the first portion.
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Patent Agency Ranking
公开(公告)号：US20230065925A1
公开(公告)日：2023-03-02
申请号：US17867768
申请日：2022-07-19
Applicant: Renesas Electronics Corporation.
Inventor： Makoto KOSHIMIZU , Yasutaka NAKASHIBA , Tohru KAWAI
Abstract: A semiconductor substrate has a surface and a convex portion projecting upward from the surface. An n-type drift region has a portion located in the convex portion. The n−-type drain region has a higher n-type impurity concentration than the n-type drift region, and is arranged in the convex portion and on the n-type drift region such that the n−-type drain region and a gate electrode sandwich the n-type drift region in plan view.
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公开(公告)号：US20210366827A1
公开(公告)日：2021-11-25
申请号：US17231623
申请日：2021-04-15
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Shinichi UCHIDA , Yasutaka NAKASHIBA , Shinichi KUWABARA
IPC: H01L23/522 , H01L23/00 , H01F27/28
Abstract: A semiconductor device includes: a first substrate; a multilayer wiring layer formed on the first substrate; a first inductor formed into a meander shape on the multilayer wiring layer in a plan view; and a second inductor formed into a meander shape on the multilayer wiring layer in a plain view, and arranged so as to be close to the first inductor in a plan view and not to overlap with the first inductor. A transformer is configured by the first inductor and the second inductor and, in a plan view, the first inductor and the second inductor extend along a first direction in which one side of the first substrate extends.
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公开(公告)号：US20210356660A1
公开(公告)日：2021-11-18
申请号：US16874176
申请日：2020-05-14
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Tetsuya IIDA , Yasutaka NAKASHIBA
Abstract: A semiconductor device includes a first insulating film, a first optical waveguide and a second optical waveguide. The first insulating film has a first surface and a second surface opposite to the first surface. The first optical waveguide is formed on the first surface of the first insulating film. The second optical waveguide is formed on the second surface of the first insulating film. The second optical waveguide, in plan view, overlaps with an end portion of the first optical waveguide without overlapping with another end portion of the first optical waveguide.
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公开(公告)号：US20210143112A1
公开(公告)日：2021-05-13
申请号：US16681329
申请日：2019-11-12
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Yasutaka NAKASHIBA
Abstract: A semiconductor device includes a semiconductor substrate, a multilayer wiring layer, a first inductor element, and a first capacitor element. The multilayer wiring layer is formed on the semiconductor substrate. The first inductor element and the first capacitor element are formed in the multilayer wiring layer. The first capacitor element is formed in the same layer as a layer in which the first inductor element is formed. The first capacitor element is formed inside the first inductor element in plan view.
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公开(公告)号：US20200287108A1
公开(公告)日：2020-09-10
申请号：US16811910
申请日：2020-03-06
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Seigo NAMIOKA , Yasutaka NAKASHIBA
Abstract: A semiconductor device includes a substrate, an optical element, and a semiconductor element. The substrate includes a first region and a second region which are regions differing from each other. The optical element is formed in one of the first region and the second region. The electric element is formed in another of the first region and the second region. The first region includes a first insulating layer and a first semiconductor layer formed on the first insulating layer. The second region includes the first insulating layer, the first semiconductor layer, a second insulating layer formed on the first semiconductor layer, and a second semiconductor layer formed on the second insulating layer.
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