公开(公告)号：US06376284B1

公开(公告)日：2002-04-23

申请号：US09570614

申请日：2000-05-12

申请人： Fernando Gonzalez ,  Gurtej S. Sandhu ,  Mike P. Violette

发明人： Fernando Gonzalez ,  Gurtej S. Sandhu ,  Mike P. Violette

IPC分类号： H01L2182

CPC分类号： H01L21/76804 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

摘要： A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal scheme wherein the strapping layer is a second metal layer overlying metal wordlines. In a method of a first embodiment the strapping material is electrically connected to the digit line through a planar landing pad overlying the conductive plug. An insulative material is sloped to the planar landing pad in order to provide a surface conducive to the formation of the strapping material. In a method of a second embodiment diodes are formed, each having a maximum width equal to f, which is equal to the minimum photolithographic limit of the photolithographic equipment being used, and distanced one from the other along a length of the digit line by a maximum distance equal to f; at least portions of the diodes are masked; at least a portion of an insulative material interposed between two diodes is removed to expose the buried digit line; and the conductive plug is formed in contact with the exposed portion of the buried digit line. After the formation of a programmable resistor in series with the diode a wordline is formed in electrical communication with each of the programmable resistors, and an insulative layer is formed overlying each wordline. Next an insulative spacer layer is deposited and etched to expose the conductive plug. The strapping layer is then formed overlying and in contact with the conductive plug.

摘要翻译： 一种存储器件，其中二极管串联连接到可编程电阻并与埋地数字线电连通。 导电插头电插入数字线和捆扎层之间，从而产生双金属方案，其中捆扎层是覆盖金属字线的第二金属层。 在第一实施例的方法中，捆扎材料通过覆盖在导电插塞上的平面着陆垫电连接到数字线。 绝缘材料倾斜到平面着陆垫，以提供有利于形成捆扎材料的表面。 在第二实施例的方法中，形成二极管，每个二极管具有等于f的最大宽度，其等于所使用的光刻设备的最小光刻极限，并且沿着数字线的长度彼此间隔一个 最大距离等于f; 二极管的至少部分被掩蔽; 插入在两个二极管之间的绝缘材料的至少一部分被去除以露出掩埋的数字线; 并且导电插塞形成为与掩埋的数字线的暴露部分接触。 在与二极管串联形成可编程电阻器之后，形成与每个可编程电阻器电连通的字线，并且在每个字线上形成绝缘层。 接下来，沉积和蚀刻绝缘间隔层以暴露导电插塞。 然后将捆扎层覆盖并与导电塞接触。

公开(公告)号：US06323088B1

公开(公告)日：2001-11-27

申请号：US09650078

申请日：2000-08-29

申请人： Fernando Gonzalez ,  Francis L. Bensistant

发明人： Fernando Gonzalez ,  Francis L. Bensistant

IPC分类号： H01L21336

CPC分类号： G11C16/0475 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0458 ,  G11C2211/5612 ,  H01L29/66825 ,  H01L29/7887

摘要： A flash memory cell in the form of a transistor capable of storing multi-bit binary data is disclosed. A pair of floating gates are provided beneath a control gate. The control gate is connected to a word line while active doped regions (source and drain regions) are connected to respective digit lines. The floating gates are separately charged and read out by controlling voltages applied to the word line and digit lines. The read out charges are decoded into a multi-bit binary value. One or both of the floating gates has a side insulator which connects through a conductor to an associated active doped region thereby forming a capacitor across the side insulator between the floating gate. This capacitor and active region facilitates operation of the transistor as a flash memory cell. Methods of fabricating the memory cell and operating it are also disclosed.

公开(公告)号：US06287937B1

公开(公告)日：2001-09-11

申请号：US09619777

申请日：2000-07-20

申请人： Roger Lee ,  Fernando Gonzalez

发明人： Roger Lee ,  Fernando Gonzalez

IPC分类号： H01L2176

CPC分类号： H01L21/76237

摘要： The present invention relates to a well-drive process in which the process of well driving is carried out simultaneously with a densification cycle. The inventive method is particularly applicable to isolation trenches having widths at or below about 0.2 microns. The inventive method may be applied to other semiconductive structures of varying geometries.

摘要翻译： 本发明涉及一种井驱动方法，其中井致动过程与致密化循环同时进行。 本发明的方法特别适用于具有等于或小于约0.2微米的宽度的隔离沟槽。 本发明的方法可以应用于不同几何形状的其他半导体结构。

公开(公告)号：US06277731B1

公开(公告)日：2001-08-21

申请号：US09584256

申请日：2000-05-31

申请人： Fernando Gonzalez ,  Guy Blalock ,  Kirk Prall

发明人： Fernando Gonzalez ,  Guy Blalock ,  Kirk Prall

IPC分类号： H01L214763

CPC分类号： H01L23/5283 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

摘要翻译： 形成连接的方法包括沉积下导体的步骤。 电介质层沉积在下导体上，电介质层具有与下导体相邻的下表面，并具有上表面。 形成在电介质层的上表面和下表面之间延伸的开口。 导电插塞沉积在开口内，插头具有接近电介质层的上表面的上表面。 上表面具有插头的上表面与电介质层相邻的边缘。 在插头的上表面的边缘附近形成凹部，凹部延伸到插塞和介电层两者中。 最后，在电介质层的上表面和插头的上表面上沉积上导体。 还公开了如此形成的连接。

公开(公告)号：US06259144B1

公开(公告)日：2001-07-10

申请号：US09558887

申请日：2000-04-26

申请人： Fernando Gonzalez

发明人： Fernando Gonzalez

IPC分类号： H01L2976

CPC分类号： H01L29/42376 ,  H01L21/28061 ,  H01L21/28114 ,  H01L28/84

摘要： A electrical device is formed by methods that are disclosed for the fabrication thereof, the electrical devices being novel polysilicon structures having increased surface areas to achieve lower resistances after silicidation. The structures are applicable, for example, to semiconductor interconnects, polysilicon gate, and capacitor applications. The inventive method provides additional means of obtaining suitable sheet resistivity and resistances for deep submicron applications. Techniques are disclosed for improving the conductivities of a silicided gate structure, a silicided interconnect structure, and capacitor component structures, each of such are situated on a substrate assembly, such as a semiconductor wafer.

摘要翻译： 电气装置由公开的用于制造电气装置的方法形成，电气装置是具有增加的表面积的新型多晶硅结构，以在硅化后实现较低的电阻。 该结构可应用于例如半导体互连，多晶硅栅极和电容器应用。 本发明的方法为深亚微米应用提供了获得合适的薄层电阻率和电阻的附加手段。 公开了用于改善硅化栅结构，硅化物互连结构和电容器组件结构的电导率的技术，其中每一个都位于诸如半导体晶片的衬底组件上。

公开(公告)号：US06204106B1

公开(公告)日：2001-03-20

申请号：US09191235

申请日：1998-11-13

申请人： Fernando Gonzalez

发明人： Fernando Gonzalez

IPC分类号： H01L218242

CPC分类号： H01L27/10844 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10894 ,  Y10S148/116 ,  Y10S438/981

摘要： The process comprises the steps of growing a first oxide layer on the upper surface of a substrate; depositing a silicon nitride layer on top of the first oxide layer; patterning the silicon nitride layer with a photoresist mask to define field oxide areas; stripping the oxide layer and regrowing a pad oxide layer on the upper surfaces of the substrate not covered by the remnants of the silicon nitride layer; removing the remnants of the silicon nitride layer; stripping the pad oxide layer and growing a sacrificial oxide layer; masking the sacrificial oxide layer with a photoresist to protect the area where the memory array will be formed; stripping the sacrificial oxide not protected by the photoresist; stripping the photoresist; and growing a gate oxide layer which is thinner than the sacrificial oxide layer. Thereafter, fabrication of the memory device may be completed using any known prior art techniques.

摘要翻译： 该方法包括在衬底的上表面上生长第一氧化物层的步骤; 在第一氧化物层的顶部上沉积氮化硅层; 用光致抗蚀剂掩模图案化氮化硅层以限定场氧化物区域; 剥离氧化物层并在衬底的上表面上再沉积未被氮化硅层的残余物覆盖的衬垫氧化物层; 去除氮化硅层的残余物; 去除衬垫氧化物层并生长牺牲氧化物层; 用光致抗蚀剂掩蔽牺牲氧化物层以保护将形成存储器阵列的区域; 剥离未被光致抗蚀剂保护的牺牲氧化物; 剥离光刻胶; 并且生长比牺牲氧化物层薄的栅极氧化物层。 此后，可以使用任何已知的现有技术来完成存储器件的制造。

公开(公告)号：US06194746B1

公开(公告)日：2001-02-27

申请号：US09150317

申请日：1998-09-09

申请人： Fernando Gonzalez ,  Tyler A. Lowrey ,  Trung Tri Doan ,  Raymond A. Turi ,  Graham R. Wolstenholme

发明人： Fernando Gonzalez ,  Tyler A. Lowrey ,  Trung Tri Doan ,  Raymond A. Turi ,  Graham R. Wolstenholme

IPC分类号： H01L2100

CPC分类号： H01L29/66136 ,  H01L27/0814 ,  H01L29/861 ,  Y10S257/91 ,  Y10S438/979

摘要： A vertical diode is provided having a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

摘要翻译： 提供了具有延伸穿过绝缘层并与硅晶片上的有源区接触的二极管开口的垂直二极管。 硅化钛层覆盖二极管开口的内表面并接触有源区。 二极管开口最初填充有非晶硅插塞，其在沉积期间被掺杂，随后再结晶以形成大晶粒多晶硅。 硅插头具有重掺杂有第一类型掺杂剂的顶部部分和轻掺杂有第二类型掺杂剂的底部部分。 顶部由底部界定，以便不与硅化钛层接触。 对于垂直二极管的一个实施例，可编程电阻器接触硅插头的顶部并且金属线接触可编程电阻器。

公开(公告)号：US06180500B2

公开(公告)日：2001-01-30

申请号：US09181461

申请日：1998-10-28

申请人： Michael P. Violette ,  Fernando Gonzalez

发明人： Michael P. Violette ,  Fernando Gonzalez

IPC分类号： H01L213205

CPC分类号： H01L21/76831 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/32139 ,  H01L21/76895 ,  H01L28/20

摘要： A method of creating ultra-small nibble structures using a modification of an already existing mask is comprised of the steps of depositing a layer of nitride on a circuit being fabricated according to standard MOSFET process steps. A layer of photoresist is patterned using a modification of an existing mask, such as a contact mask modified to include a nibble pattern. The nitride layer and an underlying oxide layer are removed according to the patterned photoresist to create a contact opening and an opening over the field oxide. Spacers may be created in the opening over the field oxide. A conductive layer and a polysilicon layer exposed in the opening over the field oxide are removed extending the opening down to the field oxide to create a nibble structure in the polysilicon layer.

摘要翻译： 使用已经存在的掩模的修改来创建超小型半字节结构的方法包括在根据标准MOSFET工艺步骤制造的电路上沉积氮化物层的步骤。 使用现有掩模的修改，例如修改为包括半字节图案的接触掩模，对光致抗蚀剂层进行图案化。 根据图案化的光致抗蚀剂去除氮化物层和下面的氧化物层，以在场氧化物上形成接触开口和开口。 可以在场氧化物的开口中产生间隔。 去除暴露在场氧化物上的开口中的导电层和多晶硅层，将开口向下延伸到场氧化物，以在多晶硅层中产生半字节结构。

公开(公告)号：US6124173A

公开(公告)日：2000-09-26

申请号：US940309

申请日：1997-09-30

申请人： Fernando Gonzalez ,  David Y. Kao

发明人： Fernando Gonzalez ,  David Y. Kao

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/336

CPC分类号： H01L27/10873 ,  H01L27/10808

摘要： A MOS gate and associated source/drain region structure providing three junction diodes between a source/drain contact area and the substrate, instead of the typical total of one, resulting in improved isolation of a source/drain contact area and a storage node which may be formed thereat. For fabricate the structure, a source/drain region is formed in a substrate having a space charge in the bulk or major part thereof, the source/drain region including: a first region having a space charge with a polarity opposite that of a space charge in the major part of the substrate; a second region separated from the major part of the substrate by the first region and having a space charge with a polarity opposite that of the space charge of the first region; and a third region separated from the first region and the major part of the substrate by the second region and having a space charge with a polarity opposite that of the space charge of the second region. The first and second regions extend laterally under an associated gate. The third region extends laterally to the boundary of the region under the gate, and does not extend under the gate. The third region includes a portion of the surface of the substrate corresponding to a source/drain contact area. The source/drain region may be prepared by successive angled implants of alternating polarity. A storage node may then be formed above the third region.

摘要翻译： 一个MOS栅极和相关的源极/漏极区域结构，在源极/漏极接触区域和衬底之间提供三个结二极管，而不是典型的总共一个，从而改善了源/漏接触区域和存储节点的隔离， 在那里形成。 为了制造该结构，在其主体或主要部分中具有空间电荷的衬底中形成源极/漏极区域，源极/漏极区域包括：具有极性与空穴电荷极性相反的空间电荷的第一区域 在基材的主要部分; 第二区域，通过所述第一区域与所述衬底的主要部分分离并且具有极性与所述第一区域的空间电荷极性相反的空间电荷; 以及通过所述第二区域与所述第一区域和所述衬底的主要部分分离并且具有极性与所述第二区域的空间电荷极性相反的空间电荷的第三区域。 第一和第二区域横向延伸在相关门下。 第三区域横向延伸到栅极下方的区域的边界处，并且不延伸到栅极下方。 第三区域包括对应于源极/漏极接触区域的衬底表面的一部分。 源极/漏极区域可以通过交替极性的连续倾斜的植入物来制备。 然后可以在第三区域上方形成存储节点。

公开(公告)号：US06111264A

公开(公告)日：2000-08-29

申请号：US970180

申请日：1997-11-13

申请人： Graham R. Wolstenholme ,  Steven T. Harshfield ,  Raymond A. Turi ,  Fernando Gonzalez ,  Guy T. Blalock ,  Donwon Park

发明人： Graham R. Wolstenholme ,  Steven T. Harshfield ,  Raymond A. Turi ,  Fernando Gonzalez ,  Guy T. Blalock ,  Donwon Park

IPC分类号： H01L27/24 ,  H01L45/00 ,  H01L47/00

CPC分类号： H01L45/1691 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144

摘要： A method for fabricating an ultra-small pore or contact for use in chalcogenide memory cells specifically and in semiconductor devices generally in which disposable spacers are utilized to fabricate ultra-small pores or contacts. The pores thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms. The pores thus defined may then be used to fabricate a chalcogenide memory cell or other semiconductor devices.

摘要翻译： 特别是制造用于硫族化物记忆体的超小孔或接触物的方法，其特征在于半导体器件中，其中一次性间隔物用于制造超小孔或接触。 如此限定的孔具有约500至4000埃的最小横向尺寸。 然后可以将如此限定的孔用于制造硫族化物存储器单元或其它半导体器件。