公开(公告)号：US11929437B2

公开(公告)日：2024-03-12

申请号：US17500020

申请日：2021-10-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Daisuke Matsubayashi ,  Keisuke Murayama

IPC: H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/7831

Abstract: A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor.

公开(公告)号：US11804407B2

公开(公告)日：2023-10-31

申请号：US17518614

申请日：2021-11-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Toshihiko Takeuchi ,  Tsutomu Murakawa ,  Hiroki Komagata ,  Daisuke Matsubayashi ,  Noritaka Ishihara ,  Yusuke Nonaka

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/786 ,  H10B12/00

CPC classification number: H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/7869 ,  H10B12/00

Abstract: A semiconductor device which has favorable electrical characteristics and can be highly integrated is provided.
The semiconductor device includes a first insulator; an oxide over the first insulator; a second insulator over the oxide; a first conductor over the second insulator; a third insulator in contact with a top surface of the first insulator, a side surface of the oxide, a top surface of the oxide, a side surface of the second insulator, and a side surface of the first conductor; and a fourth insulator over the third insulator. The third insulator includes an opening exposing the first insulator, and the fourth insulator is in contact with the first insulator through the opening.

公开(公告)号：US11696455B2

公开(公告)日：2023-07-04

申请号：US17509157

申请日：2021-10-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takanori Matsuzaki ,  Yoshinobu Asami ,  Daisuke Matsubayashi ,  Tatsuya Onuki

IPC: H01L27/105 ,  H01L27/12 ,  H01L29/786 ,  H10B99/00

CPC classification number: H10B99/00 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1244 ,  H01L27/1255 ,  H01L29/7869 ,  H01L29/78648 ,  H01L29/78696

Abstract: A first transistor, a second transistor, a capacitor, and first to third conductors are included. The first transistor includes a first gate, a source, and a drain. The second transistor includes a second gate, a third gate over the second gate, first and second low-resistance regions, and an oxide sandwiched between the second gate and the third gate. The capacitor includes a first electrode, a second electrode, and an insulator sandwiched therebetween. The first low-resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate and is connected to a bottom surface of the first low-resistance region. The capacitor overlaps with the first low-resistance region. The second conductor is electrically connected to the drain. The third conductor overlaps with the second conductor and is connected to the second conductor and a side surface of the second low-resistance region.

公开(公告)号：US11152494B2

公开(公告)日：2021-10-19

申请号：US16878758

申请日：2020-05-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Junichi Koezuka ,  Yukinori Shima ,  Hajime Tokunaga ,  Toshinari Sasaki ,  Keisuke Murayama ,  Daisuke Matsubayashi

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/51 ,  H01L29/786 ,  H01L27/12

Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor device including an oxide semiconductor film. In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.

公开(公告)号：US11056491B2

公开(公告)日：2021-07-06

申请号：US16623648

申请日：2018-06-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Daisuke Matsubayashi ,  Tatsuya Onuki

IPC: H01L27/105 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L21/4757 ,  H01L29/24 ,  H01L29/66 ,  H01L21/477

Abstract: A semiconductor device that can be highly integrated is provided. The semiconductor device includes a transistor, an interlayer film, and a first conductor. The transistor includes an oxide over a first insulator; a second conductor over the oxide; a second insulator provided between the oxide and the second conductor and in contact with a side surface of the second conductor; and a third insulator provided for the side surface of the second conductor with the second insulator therebetween. The oxide includes a first region, a second region, and a third region. The first region overlaps with the second conductor. The second region is provided between the first region and the third region. The third region has a lower resistance than the second region. The second region has a lower resistance than the first region. The interlayer film is provided over the first insulator and the oxide. The first conductor is electrically connected to the third region. The third region overlaps with one of the third insulator, the first conductor, and the interlayer film. A top surface of the third insulator is level with a top surface of the interlayer film.

公开(公告)号：US10553690B2

公开(公告)日：2020-02-04

申请号：US15220498

申请日：2016-07-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro Tanaka ,  Kazuki Tanemura ,  Daisuke Matsubayashi

IPC: H01L29/786 ,  H01L29/40 ,  H01L49/02 ,  H01L27/06

Abstract: A miniaturized transistor with reduced parasitic capacitance and highly stable electrical characteristics is provided. High performance and high reliability of a semiconductor device including the transistor is achieved. A first conductor is formed over a substrate, a first insulator is formed over the first conductor, a layer that retains fixed charges is formed over the first insulator, a second insulator is formed over the layer that retains fixed charges, and a transistor is formed over the second insulator. Threshold voltage Vth is controlled by appropriate adjustment of the thicknesses of the first insulator, the second insulator, and the layer that retains fixed charges.

公开(公告)号：US20180233588A1

公开(公告)日：2018-08-16

申请号：US15947902

申请日：2018-04-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kazutaka Kuriki ,  Yuji Egi ,  Hiromi Sawai ,  Yusuke Nonaka ,  Noritaka Ishihara ,  Daisuke Matsubayashi

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L29/66969 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02565 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1259 ,  H01L27/1262 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: Provided is a semiconductor device having favorable reliability. A manufacturing method of a semiconductor device comprising the steps of: forming a first oxide semiconductor having an island shape; forming a first conductor and a second conductor over the first oxide semiconductor; forming an oxide semiconductor film over the first oxide semiconductor, the first conductor, and the second conductor; forming a first insulating film over the oxide semiconductor film; forming a conductive film over the first insulating film; removing part of the first insulating film and part of the conductive film to form a first insulator and a third conductor; forming a second insulating film covering the first insulator and the third conductor; removing part of the oxide semiconductor film and part of the second insulating film to form a second oxide semiconductor and a second insulator and to expose a side surface of the first oxide semiconductor; forming a third insulator in contact with the side surface of the first oxide semiconductor and with a side surface of the second oxide semiconductor; forming a fourth insulator in contact with the third insulator; and performing a microwave-excited plasma treatment to the third insulator and the fourth insulator.

公开(公告)号：US20180197997A1

公开(公告)日：2018-07-12

申请号：US15864033

申请日：2018-01-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo ITO ,  Daisuke Matsubayashi ,  Masaharu Nagai ,  Yoshiaki Yamamoto ,  Takashi Hamada ,  Yutaka Okazaki ,  Shinya Sasagawa ,  Motomu Kurata ,  Naoto Yamade

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/425 ,  H01L21/46 ,  H01L27/12

CPC classification number: H01L29/78693 ,  H01L21/425 ,  H01L21/46 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7782 ,  H01L29/7854 ,  H01L29/7855 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).

公开(公告)号：US09947777B2

公开(公告)日：2018-04-17

申请号：US15492253

申请日：2017-04-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kazutaka Kuriki ,  Yuji Egi ,  Hiromi Sawai ,  Yusuke Nonaka ,  Noritaka Ishihara ,  Daisuke Matsubayashi

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L27/12

CPC classification number: H01L29/66969 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02565 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/1262 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: Provided is a semiconductor device having favorable reliability. A manufacturing method of a semiconductor device comprising the steps of: forming a first oxide semiconductor having an island shape; forming a first conductor and a second conductor over the first oxide semiconductor; forming an oxide semiconductor film over the first oxide semiconductor, the first conductor, and the second conductor; forming a first insulating film over the oxide semiconductor film; forming a conductive film over the first insulating film; removing part of the first insulating film and part of the conductive film to form a first insulator and a third conductor; forming a second insulating film covering the first insulator and the third conductor; removing part of the oxide semiconductor film and part of the second insulating film to form a second oxide semiconductor and a second insulator and to expose a side surface of the first oxide semiconductor; forming a third insulator in contact with the side surface of the first oxide semiconductor and with a side surface of the second oxide semiconductor; forming a fourth insulator in contact with the third insulator; and performing a microwave-excited plasma treatment to the third insulator and the fourth insulator.

公开(公告)号：US09871145B2

公开(公告)日：2018-01-16

申请号：US15628699

申请日：2017-06-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo Ito ,  Daisuke Matsubayashi ,  Masaharu Nagai ,  Yoshiaki Yamamoto ,  Takashi Hamada ,  Yutaka Okazaki ,  Shinya Sasagawa ,  Motomu Kurata ,  Naoto Yamade

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786 ,  H01L29/66 ,  H01L21/425 ,  H01L21/46 ,  H01L27/12

CPC classification number: H01L29/78693 ,  H01L21/425 ,  H01L21/46 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7782 ,  H01L29/7854 ,  H01L29/7855 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).