公开(公告)号：US20210143281A1

公开(公告)日：2021-05-13

申请号：US17010151

申请日：2020-09-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Hiroyuki MIYAKE ,  Kei TAKAHASHI ,  Kouhei TOYOTAKA ,  Masashi TSUBUKU ,  Kosei NODA ,  Hideaki KUWABARA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/26 ,  G06K19/077 ,  H01L21/8236 ,  H01L23/66 ,  H01L27/088 ,  H01L29/24 ,  H01L29/66

Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

公开(公告)号：US20210132672A1

公开(公告)日：2021-05-06

申请号：US17145436

申请日：2021-01-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA ,  Shunpei YAMAZAKI

IPC: G06F1/26 ,  G06F1/3287

Abstract: To individually control supply of the power supply voltage to circuits, a semiconductor device includes a CPU, a memory that reads and writes data used in arithmetic operation of the CPU, a signal processing circuit that generates an output signal by converting a data signal generated by the arithmetic operation of the CPU, a first power supply control switch that controls supply of the power supply voltage to the CPU, a second power supply control switch that controls supply of the power supply voltage to the memory, a third power supply control switch that controls supply of the power supply voltage to the signal processing circuit, and a controller that at least has a function of controlling the first to third power supply control switches individually in accordance with an input signal and instruction signals input from the CPU and the signal processing circuit.

公开(公告)号：US20210020125A1

公开(公告)日：2021-01-21

申请号：US17030616

申请日：2020-09-24

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Yoshiharu HIRAKATA

IPC: G09G3/36 ,  G02F1/1335 ,  G02F1/1368

Abstract: To provide a liquid crystal display device which can perform image display in both modes: a reflective mode where external light is used as an illumination light source; and a transmissive mode where a backlight is used. In one pixel, a region where incident light through a liquid crystal layer is reflected to perform display (reflective region) and a region through which light from the backlight passes to perform display (transmissive region) are provided, and image display can be performed in both modes: the reflective mode where external light is used as an illumination light source; and the transmissive mode where the backlight is used as an illumination light source. In addition, two transistors connected to respective pixel electrode layers are provided in one pixel, and the two transistors are separately operated, whereby display of the reflective region and display of the transmissive region can be controlled independently.

公开(公告)号：US20200342915A1

公开(公告)日：2020-10-29

申请号：US16882064

申请日：2020-05-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Jun KOYAMA ,  Shunpei YAMAZAKI

IPC: G11C5/10 ,  G11C7/12 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/02 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  G11C7/18

Abstract: An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.

公开(公告)号：US20200219905A1

公开(公告)日：2020-07-09

申请号：US16823744

申请日：2020-03-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Hiroyuki MIYAKE

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H01L29/04 ,  H01L27/088

Abstract: An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

公开(公告)号：US20200043382A1

公开(公告)日：2020-02-06

申请号：US16340227

申请日：2017-10-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Toshiyuki ISA ,  Akio ENDO ,  Yosuke TSUKAMOTO ,  Jun KOYAMA

IPC: G09F9/30 ,  G06F1/16

Abstract: An electronic device including a large display region and with improved portability is provided. An electronic device with improved reliability is provided.An information processing device includes a first film, a panel substrate, and at least a first housing. The panel substrate has flexibility and a display region, and the first film has a visible-light-transmitting property and flexibility. The first housing includes a first slit, the panel substrate includes a region positioned between the first film and a second film, the first slit has a function of storing the region, and one or both of the panel substrate and the first film can slide along the first slit.

公开(公告)号：US20180350998A1

公开(公告)日：2018-12-06

申请号：US16053200

申请日：2018-08-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Masahiro TAKAHASHI ,  Hideyuki KISHIDA ,  Akiharu MIYANAGA ,  Junpei SUGAO ,  Hideki UOCHI ,  Yasuo NAKAMURA

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L29/49 ,  H01L29/45 ,  H01L29/423 ,  H01L29/24 ,  H01L27/12 ,  H01L21/768 ,  H01L21/324

CPC classification number: H01L29/7869 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/324 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76838 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606

Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.

公开(公告)号：US20180059466A1

公开(公告)日：2018-03-01

申请号：US15792841

申请日：2017-10-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA

IPC: G02F1/1362 ,  G09G3/36

CPC classification number: G02F1/13624 ,  G09G3/3659 ,  G09G2300/0852

Abstract: A liquid crystal display device with a novel structure is provided. Each pixel includes a first circuit for holding a high level (or low level) potential and a second circuit for holding a low level (or high level) potential. A semiconductor layer of a transistor included in each of the first and second circuits is an oxide semiconductor layer. The second circuit is reset when being supplied with the high level potential. Whether the high level potential held in the second circuit changes is controlled by a data voltage supplied to the first circuit. The potential held in the first circuit and the potential held in the second circuit are respectively supplied to a first transistor and a second transistor.

公开(公告)号：US20170315589A1

公开(公告)日：2017-11-02

申请号：US15497743

申请日：2017-04-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Toshiyuki ISA ,  Akio ENDO ,  Yosuke TSUKAMOTO ,  Jun KOYAMA

IPC: G06F1/16 ,  G06F3/044 ,  G06F3/041

CPC classification number: G06F1/1652 ,  G06F1/1616 ,  G06F1/1618 ,  G06F1/1641 ,  G06F1/1675 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/042 ,  G06F3/044 ,  G06F2203/04102 ,  G06F2203/04103 ,  G06F2203/04111 ,  H01L27/323

Abstract: An electronic device with a large display region and improved portability is provided. An electronic device with improved reliability is provided. The information processing device includes a first film, a second film, a panel substrate, and at least a first housing. The panel substrate has flexibility and includes a display region. The first film has visible light transmittance and flexibility, and the second film has flexibility. The first housing includes a first slit, the panel substrate includes a region interposed between the first film and the second film, the first slit is configured to store the region, and one or more of the panel substrate, the first film, and the second film can slide along the first slit.

公开(公告)号：US20170301380A1

公开(公告)日：2017-10-19

申请号：US15635550

申请日：2017-06-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: G11C7/10 ,  H01L27/12 ,  H01L27/06 ,  H01L23/528 ,  G11C8/08 ,  G11C7/22 ,  G11C7/18 ,  H01L29/786 ,  G11C7/12

CPC classification number: G11C7/10 ,  G11C5/06 ,  G11C5/147 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/08 ,  G11C11/24 ,  G11C11/4097 ,  G11C16/0433 ,  G11C16/28 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/22 ,  H01L29/24 ,  H01L29/26 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile semiconductor memories which do not require specific erasing operation and do not suffer from damages due to repeated writing operation. Furthermore, the semiconductor device is well adapted to store multivalued data. Manufacturing methods, application circuits and driving/reading methods are explained in details in the description.