公开(公告)号：US20180144991A1

公开(公告)日：2018-05-24

申请号：US15874813

申请日：2018-01-18

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Pierre Morin ,  Yann Mignot

IPC: H01L21/8238 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/7842 ,  H01L29/785

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

公开(公告)号：US09917194B2

公开(公告)日：2018-03-13

申请号：US15365640

申请日：2016-11-30

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/49 ,  H01L29/06 ,  H01L29/417 ,  H01L29/10 ,  H01L29/66 ,  H01L29/161

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7849 ,  H01L2029/7858

Abstract: A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%.

公开(公告)号：US09679899B2

公开(公告)日：2017-06-13

申请号：US14833857

申请日：2015-08-24

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin ,  Yann Mignot

IPC: H01L27/092 ,  H01L29/165 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/823821 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/7842 ,  H01L29/785

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

公开(公告)号：US09647086B2

公开(公告)日：2017-05-09

申请号：US14826803

申请日：2015-08-14

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporations ,  STMicroelectronics, Inc.

Inventor： Steven Bentley ,  Jody Fronheiser ,  Xin Miao ,  Joseph Washington ,  Pierre Morin

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L21/324 ,  H01L21/306 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L29/66537 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/324 ,  H01L29/0638 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/165

Abstract: A method of performing an early PTS implant and forming a buffer layer under a bulk or fin channel to control doping in the channel and the resulting bulk or fin device are provided. Embodiments include forming a recess in a substrate; forming a PTS layer below a bottom surface of the recess; forming a buffer layer on the bottom surface and on side surfaces of the recess; forming a channel layer on and adjacent to the buffer layer; and annealing the channel, buffer, and PTS layers.

公开(公告)号：US09620626B2

公开(公告)日：2017-04-11

申请号：US14272660

申请日：2014-05-08

Applicant: Soitec ,  STMicroelectronics, Inc.

Inventor： Frédéric Allibert ,  Pierre Morin

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/205 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02614 ,  H01L21/02694 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/205

Abstract: Methods of fabricating semiconductor structures involve the formation of fins for finFET transistors having different stress/strain states. Fins of one stress/strain state may be employed to form n-type finFETS, while fins of another stress/strain state may be employed to form p-type finFETs. The fins having different stress/strain states may be fabricated from a common layer of semiconductor material. Semiconductor structures and devices are fabricated using such methods.

公开(公告)号：US09548361B1

公开(公告)日：2017-01-17

申请号：US14755663

申请日：2015-06-30

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7849 ,  H01L2029/7858

Abstract: A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%.

Abstract translation: 自对准SiGe FinFET器件具有具有高锗浓度的松弛沟道区。 不是首先将锗引入通道，然后尝试松弛所得到的应变膜，最初形成松弛的通道以接受锗。 以这种方式，可以建立锗的存在而不会使晶格变形或损坏。 在将锗引入鳍状晶格结构之前，门结构相对于本征硅散热片图案化，以确保栅极正确对准。 在对齐栅极结构之后，将硅片段分段以弹性地松弛硅晶格。 然后，将锗引入松弛的硅晶格中，以产生基本上无应力且也无缺陷的SiGe沟道。 使用所述方法，在结构稳定的膜中实现的锗的浓度可以增加到大于85％的水平。

公开(公告)号：US09543214B2

公开(公告)日：2017-01-10

申请号：US14526081

申请日：2014-10-28

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics, Inc.

Inventor： Denis Rideau ,  Elise Baylac ,  Emmanuel Josse ,  Pierre Morin ,  Olivier Nier

IPC: H01L21/8234 ,  H01L21/84 ,  H01L21/762 ,  H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/324 ,  H01L27/12

CPC classification number: H01L21/823481 ,  H01L21/02356 ,  H01L21/02532 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/3081 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/7831 ,  H01L29/7846 ,  H01L29/7847

Abstract: The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed semiconductor layer, one or more first isolation trenches in a first direction for delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in the semiconductor structure, one or more second isolation trenches in a second direction for delimiting a second dimension of the at least one transistor, the first and second isolation trenches being at least partially filled with an insulating material; and before or after the formation of the second isolation trenches, decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches, wherein atoms of the first material are not implanted into the second isolation trenches.

Abstract translation: 本发明涉及一种形成具有单轴应力的半导体层的方法，包括：在具有应力半导体层的半导体结构中形成在第一方向上的一个或多个第一隔离沟槽，以限定待形成的至少一个晶体管的第一维度 在所述半导体结构中; 在所述半导体结构中，在第二方向上形成用于限定所述至少一个晶体管的第二尺寸的一个或多个第二隔离沟槽，所述第一和第二隔离沟槽至少部分地填充有绝缘材料; 并且在形成第二隔离沟槽之前或之后，通过将第一材料的原子注入到第一隔离沟槽中来降低第一隔离沟槽中的绝缘材料的粘度，其中第一材料的原子未被注入第二隔离层 沟渠

公开(公告)号：US09431538B2

公开(公告)日：2016-08-30

申请号：US14950833

申请日：2015-11-24

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMICROELECTRONICS, Inc.

Inventor： Shay Reboh ,  Pierre Morin

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: Method of making at least one transistor strained channel semiconducting structure, comprising steps to form a sacrificial gate block and insulating spacers arranged in contact with the lateral faces of the sacrificial gate block, form sacrificial regions in contact with the lateral faces of said semiconducting zone, said sacrificial regions being configured so as to apply a strain on said semiconducting zone, remove said sacrificial gate block between said insulating spacers, replace said sacrificial gate block by a replacement gate block between said insulating spacers, remove said sacrificial regions, and replace said sacrificial regions by replacement regions in contact with the lateral faces of said semiconducting zone, on a semiconducting zone that will form a transistor channel region.

Abstract translation: 制造至少一个晶体管应变通道半导体结构的方法，包括形成牺牲栅极块的步骤和与牺牲栅极块的侧面接触地布置的绝缘间隔物，形成与所述半导体区域的侧面接触的牺牲区域， 所述牺牲区域被配置为在所述半导体区域上施加应变，去除所述绝缘间隔物之间​​的所述牺牲栅极块，用所述绝缘间隔物之间​​的置换栅极块代替所述牺牲栅极块，去除所述牺牲区域， 区域，其与形成晶体管沟道区域的半导体区域相接触，与所述半导体区域的侧面接触。

公开(公告)号：US20160035820A1

公开(公告)日：2016-02-04

申请号：US14447678

申请日：2014-07-31

Applicant: STMicroelectronics, Inc. ,  Commissariat a l'Energie Atomique et aux Energies Alternatives ,  GLOBALFOUNDRIES Inc.

Inventor： Pierre Morin ,  Maud Vinet ,  Laurent Grenouillet ,  Ajey Poovannummoottil Jacob

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0607 ,  H01L21/02636 ,  H01L21/283 ,  H01L21/3086 ,  H01L21/32 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/1066 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.

公开(公告)号：US09240466B2

公开(公告)日：2016-01-19

申请号：US14451174

申请日：2014-08-04

Applicant: STMicroelectronics SA ,  STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Denis Rideau ,  Olivier Nier

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L21/762 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L29/66772 ,  H01L21/0217 ,  H01L21/324 ,  H01L21/76283 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/785

Abstract: The disclosure concerns a method of stressing a semiconductor layer comprising: forming, over a silicon on insulator structure having a semiconductor layer in contact with an insulating layer, one or more stressor blocks aligned with first regions of said semiconductor layer in which transistor channels are to be formed, wherein said stressor blocks are stressed such that they locally stress said semiconductor layer; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.

Abstract translation: 本公开涉及一种对半导体层施加应力的方法，包括：在绝缘体上的结构上形成绝缘体结构，该绝缘体上硅结构具有与绝缘层相接触的半导体层，一个或多个与晶体管沟道所在半导体层的第一区对准的应力块 形成，其中所述应力块被应力，使得它们局部应力所述半导体层; 以及通过退火所述绝缘体层的粘度暂时减小所述绝缘层的与所述第一区域相邻的第二区域。