公开(公告)号：US20240126170A1

公开(公告)日：2024-04-18

申请号：US18200495

申请日：2023-05-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Chih HO ,  Chin-Hsiang Lin ,  Ching-Yu Chang

IPC: G03F7/038 ,  G03F7/20 ,  H01L21/027

CPC classification number: G03F7/0382 ,  G03F7/2004 ,  H01L21/0275

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer including a photoresist composition over a substrate. The photoresist layer is selectively exposed to actinic radiation, the selectively exposed photoresist layer is developed to form a pattern in the photoresist layer. The photoresist composition includes a polymer including monomer units with photocleaving promoters, wherein the photocleaving promoters are one or more selected from the group consisting of living free radical polymerization chain transfer agents, electron withdrawing groups, bulky two dimensional (2-D) or three dimensional (3-D) organic groups, N-(acyloxy)phthalimides, and electron stimulated radical generators.

公开(公告)号：US20240118618A1

公开(公告)日：2024-04-11

申请号：US18133933

申请日：2023-04-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Chih HO ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/075 ,  H01L21/027

CPC classification number: G03F7/0757 ,  H01L21/0276

Abstract: A method of manufacturing a semiconductor device includes forming a first layer having an organic material over a substrate. A second layer is formed over the first layer, wherein the second layer includes a silicon-containing polymer having pendant acid groups or pendant photoacid generator groups. The forming a second layer includes: forming a layer of a composition including a silicon-based polymer and a material containing an acid group or photoacid generator group over the first layer, floating the material containing an acid group or photoacid generator group over the silicon-based polymer, and reacting the material containing an acid group or photoacid generator group with the silicon-based polymer to form an upper second layer including a silicon-based polymer having pendant acid groups or pendant photoacid generator groups overlying a lower second layer comprising the silicon-based polymer. A photosensitive layer is formed over the second layer, and the photosensitive layer is patterned.

公开(公告)号：US11656553B2

公开(公告)日：2023-05-23

申请号：US17315595

申请日：2021-05-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Li-Yen Lin ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/20 ,  G03F7/16 ,  H01L21/311 ,  H01L21/033 ,  G03F7/09 ,  G03F7/039 ,  H01L21/027 ,  G03F7/004

CPC classification number: G03F7/70025 ,  G03F7/0045 ,  G03F7/0397 ,  G03F7/094 ,  G03F7/168 ,  G03F7/70033 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/31105 ,  H01L21/31144

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate and forming a resist layer over the material layer. The method includes exposing a portion of the resist layer. The resist layer includes a photoacid generator (PAG) group, a quencher group, an acid-labile group (ALG) and a polar unit (PU). The method also includes performing a baking process on the resist layer and developing the resist layer to form a patterned resist layer. The method further includes doping a portion of the material layer by using the patterned resist layer as a mask to form a doped region. In addition, the method includes removing the patterned resist layer.

公开(公告)号：US11069558B2

公开(公告)日：2021-07-20

申请号：US16713981

申请日：2019-12-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Hsiang Lin ,  Keng-Chu Lin ,  Shwang-Ming Jeng ,  Teng-Chun Tsai ,  Tsu-Hsiu Perng ,  Fu-Ting Yen

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

公开(公告)号：US10787742B2

公开(公告)日：2020-09-29

申请号：US15822469

申请日：2017-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yen-Shuo Su ,  Ying Xiao ,  Chin-Hsiang Lin

IPC: C23C16/50 ,  C23C16/455 ,  H01J37/32 ,  C23C16/52

Abstract: A control system for a plasma treatment apparatus includes a wafer treatment device. The wafer treatment device includes a vapor chamber and an upper electrode assembly. The upper electrode assembly includes a gas distribution plate having a plurality of holes. The upper electrode assembly includes an upper electrode having at least one gas nozzle and at least one controllable valve connected to the at least one gas nozzle for controlling a flow of gas from a gas supply to the holes via the at least one gas nozzle. The at least one gas nozzle is separated from the gate distribution plate by a gap. The control system includes a measurement device configured to measure a thickness profile of a wafer. The control system includes a controller configured to generate a control signal. The at least one controllable valve is configured to be adjusted based on the control signal.

公开(公告)号：US10269628B2

公开(公告)日：2019-04-23

申请号：US15444060

申请日：2017-02-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sung-Li Wang ,  Ding-Kang Shih ,  Chin-Hsiang Lin ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L29/76 ,  H01L21/768 ,  H01L29/06 ,  H01L23/485 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L21/02

Abstract: A contact structure of a semiconductor device is provided. The contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate, and wherein a surface of the strained material has received a passivation treatment; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; a metal barrier coating an opening of the dielectric layer; and a metal layer filling a coated opening of the dielectric layer.

公开(公告)号：US10161965B2

公开(公告)日：2018-12-25

申请号：US14659268

申请日：2015-03-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui-Long Chen ,  Chien-Chih Liao ,  Chin-Hsiang Lin ,  Hui-yun Chao ,  Jong-I Mou ,  Tseng Chin Lo ,  Ta-Yung Lee

IPC: G01N21/956 ,  G01R1/073 ,  H01L23/544 ,  G01R31/28 ,  G01R1/067

Abstract: A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment contacts and a probe card containing a plurality of probe points at a wafer test system. A historical offset correction is received. Based on the historical offset correct, an orientation value for the probe card relative to the wafer is determined. The probe card is aligned to the wafer using the orientation value in an attempt to bring a first probe point into contact with a first alignment contact. The connectivity of the first probe point and the first alignment contact is evaluated. An electrical test of the wafer is performed utilizing the aligned probe card, and the historical offset correction is updated based on the orientation value.

公开(公告)号：US20180151351A1

公开(公告)日：2018-05-31

申请号：US15723582

申请日：2017-10-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chang Lilin ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/027 ,  G03F7/09 ,  G03F7/20 ,  G03F7/42

CPC classification number: H01L21/0276 ,  G03F7/0045 ,  G03F7/0046 ,  G03F7/091 ,  G03F7/095 ,  G03F7/423 ,  G03F7/70

Abstract: The present disclosure provides an embodiment of a method for lithography patterning. The method includes coating a photoresist layer over a substrate, wherein the photoresist layer includes a first polymer, and a first photo-acid generator (PAG), and a chemical additive mixed in a solvent; performing an exposing process to the photoresist layer; and performing a developing process to the photoresist layer to form a patterned photoresist layer. The chemical additive has a non-uniform distribution in the photoresist layer.

公开(公告)号：US20180128597A1

公开(公告)日：2018-05-10

申请号：US15864458

申请日：2018-01-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Hsiang Tseng ,  Chin-Hsiang Lin ,  Heng-Hsin Liu ,  Jui-Chun Peng ,  Ho-Ping Chen

IPC: G01B11/02 ,  G03F9/00 ,  H01L23/544

CPC classification number: G01B11/02 ,  G03F9/7011 ,  G03F9/7084 ,  H01L23/544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wafer alignment apparatus includes a light source, a light detection device, and a rotation device configured to rotate a wafer. The light source is configured to provide a light directed to the wafer. The light detection device is configured to detect reflected light intensity from the wafer to locate at least one wafer alignment mark of wafer alignment marks separated by a plurality of angles. At least two of those angles are equal.

公开(公告)号：US09709904B2

公开(公告)日：2017-07-18

申请号：US14748543

申请日：2015-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tung-Li Wu ,  Chin-Hsiang Lin ,  Heng-Hsin Liu ,  Jui-Chun Peng

IPC: G03B27/54 ,  G03B27/72 ,  G03F7/20

CPC classification number: G03F7/70725 ,  G03F7/70066 ,  G03F7/70283 ,  G03F7/70341 ,  G03F7/70641

Abstract: A lithography apparatus includes a plurality reticle edge masking assemblies (REMAs), wherein each REMA of the plurality of REMAs is positioned to receive one of a plurality of light beams, and each REMA of the plurality of REMAs comprises a movable slit for passing the received light beam therethrough. The lithography apparatus includes a controller for controlling a speed of the movable slit based on a size of the movable slit, an intensity of the one or more collimated light beams, or a material to be patterned. The lithography apparatus further includes a single mask having a single pattern, wherein the mask is configured to receive light from every REMA of the plurality of REMAs. The lithography apparatus includes a projection lens configured to receive light transmitted through the single mask, wherein the lithography apparatus is configured to introduce an immersion liquid into a space adjacent to the projection lens.