公开(公告)号：US20190155605A1

公开(公告)日：2019-05-23

申请号：US16237547

申请日：2018-12-31

Applicant: Texas Instruments Incorporated

Inventor： Duc Quang Bui ,  Joseph Raymond Michael Zbiciak

IPC: G06F9/30 ,  G06F9/38

Abstract: In a method of operating a computer system, an instruction loop is executed by a processor in which each iteration of the instruction loop accesses a current data vector and an associated current vector predicate. The instruction loop is repeated when the current vector predicate indicates the current data vector contains at least one valid data element and the instruction loop is exited when the current vector predicate indicates the current data vector contains no valid data elements.

公开(公告)号：US20190095204A1

公开(公告)日：2019-03-28

申请号：US16203503

申请日：2018-11-28

Applicant: Texas Instruments Incorporated

Inventor： Joseph Raymond Michael Zbiciak ,  Timothy David Anderson ,  Jonathan (Son) Hung Tran ,  Kai Chirca ,  Daniel Wu ,  Abhijeet Ashok Chachad ,  David M. Thompson

IPC: G06F9/30 ,  G06F11/00 ,  G06F9/345 ,  G06F9/38 ,  G06F11/10 ,  G06F12/0897 ,  G06F9/32 ,  G06F12/0875

Abstract: A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache management operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.

公开(公告)号：US20180129608A9

公开(公告)日：2018-05-10

申请号：US14874842

申请日：2015-10-05

Applicant: Texas Instruments Incorporated

Inventor： Raguram Damodaran ,  Joseph Raymond Michael Zbiciak ,  Naveen Bhoria

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0888 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F2212/1021 ,  G06F2212/6022 ,  G06F2212/70

Abstract: The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register.

公开(公告)号：US20170097894A1

公开(公告)日：2017-04-06

申请号：US14874842

申请日：2015-10-05

Applicant: Texas Instruments Incorporated

Inventor： Raguram Damodaran ,  Joseph Raymond Michael Zbiciak ,  Naveen Bhoria

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0888 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F2212/1021 ,  G06F2212/6022 ,  G06F2212/70

Abstract: The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register.

公开(公告)号：US09298643B2

公开(公告)日：2016-03-29

申请号：US14728541

申请日：2015-06-02

Applicant: Texas Instruments Incorporated

Inventor： Jonathan (Son) Hung Tran ,  Raguram Damodaran ,  Abhijeet Ashok Chachad ,  Joseph Raymond Michael Zbiciak

IPC: G06F12/10 ,  G06F7/483 ,  G06F9/30 ,  H03M13/35 ,  H03M13/29 ,  G06F11/10 ,  G06F13/16 ,  G06F13/18 ,  H03K19/00 ,  G06F1/32 ,  H03K21/00 ,  G06F12/02 ,  G06F12/12 ,  G06F12/08 ,  G06F13/364

CPC classification number: G06F12/1081 ,  G06F1/3296 ,  G06F7/483 ,  G06F9/3012 ,  G06F11/1064 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/12 ,  G06F13/1605 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/18 ,  G06F13/364 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/221 ,  G06F2212/2532 ,  G06F2212/283 ,  G06F2212/608 ,  H03K19/0016 ,  H03K21/00 ,  H03M13/2903 ,  H03M13/353 ,  Y02D10/124 ,  Y02D10/172 ,  Y02D50/20

Abstract: This invention optimizes DMA writes to directly addressable level two memory that is cached in level one and the line is valid and dirty. When the level two controller detects that a line is valid and dirty in level one, the level two memory need not update its copy of the data. Level one memory will replace the level two copy with a victim writeback at a future time. Thus the level two memory need not store write a copy. This limits the number of DMA writes to level two directly addressable memory and thus improves performance and minimizes dynamic power. This also frees the level two memory for other master/requestors.

Abstract translation: 本发明将DMA写入优化为直接可寻址的二级存储器，该存储器缓存在一级，并且该行是有效和脏的。 当二级控制器检测到一级线路有效且脏一级时，二级存储器不需要更新其数据副本。 一级记忆将在将来的时候用受害者回写替代第二级副本。 因此，二级内存不需要存储写入副本。 这将DMA写入次数限制在二级可直接寻址的存储器中，从而提高性能并最大限度地减少动态功耗。 这也释放了其他主/请求者的二级内存。

公开(公告)号：US20150019845A1

公开(公告)日：2015-01-15

申请号：US14326969

申请日：2014-07-09

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Joseph Raymond Michael Zbiciak

IPC: G06F9/30

CPC classification number: G06F9/3853 ,  G06F9/30167

Abstract: The invention allows a processor to maintain a fixed instruction width regardless of the width of the constants needed. The constant extension solves the problem of having variable length opcodes to accommodate longer constants. The invention allows the architecture to have a fixed width, regardless of the width of the constants specified, which simplify instruction decoding. Constant widths can be variable and extend beyond the fixed processor instruction width.

Abstract translation: 本发明允许处理器维持固定的指令宽度，而与所需常数的宽度无关。 常数扩展解决了具有可变长度操作码以适应更长常数的问题。 本发明允许架构具有固定的宽度，而不管指定的常数的宽度，这简化了指令解码。 恒定宽度可以是可变的并且延伸超出固定的处理器指令宽度。

公开(公告)号：US20150006820A1

公开(公告)日：2015-01-01

申请号：US13973306

申请日：2013-08-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Joseph Raymond Michael Zbiciak ,  Raguram Damodaran ,  Abhijeet Ashok Chachad

IPC: G06F12/08

CPC classification number: G06F12/0811

Abstract: Traffic output from a cache write-miss buffer is controlled by determining whether a predetermined condition is satisfied, and outputting an oldest entry from the buffer only in response to a determination that the predetermined condition is satisfied. Posting of a new entry to the buffer is insufficient to satisfy the predetermined condition.

Abstract translation: 通过确定是否满足预定条件来控制来自高速缓存写入 - 未命中缓冲器的流量输出，并且仅响应于满足预定条件的确定从缓冲器输出最旧的条目。 向缓冲器发送新条目不足以满足预定条件。