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100 条记录 (耗时 0.018 秒)

    Differential amplifier circuit, CMOS inverter, demodulator circuit for pulse-width modulation, and sampling circuit
    71.
    发明授权
    Differential amplifier circuit, CMOS inverter, demodulator circuit for pulse-width modulation, and sampling circuit 失效
    差分放大电路，CMOS反相器，脉宽调制解调电路和采样电路

    公开(公告)号：US6094090A

    公开(公告)日：2000-07-25

    申请号：US980259

    申请日：1997-11-28

    申请人： Tadaaki Yamauchi

    发明人： Tadaaki Yamauchi

    IPC分类号： H03M1/12 ,  G11C7/06 ,  G11C11/409 ,  H03F3/45 ,  H03K5/02 ,  H03K17/687 ,  H03M1/50 ,  G05F1/10 ,  G05F3/02

    CPC分类号： H03K5/023 ,  G11C7/062 ,  G11C7/065 ,  H03M1/504

    摘要： There is disclosed a differential amplifier circuit wherein resistors (89, 91) and capacitors (90, 92) are connected respectively between sources of a differential pair of NMOS transistors (85, 87) and a power supply (2). The resistors (89, 91) raise the source potential of the NMOS transistors to reduce current flows during the time no transition of signal level outputted from the differential amplifier circuit occurs, reducing power consumption in the differential amplifier circuit. The capacitor (90, 92) alleviate the effects of voltage drop by the resistors (89, 91) during the signal level transition to prevent reduction in operating speed of the differential amplifier circuit.

    摘要翻译： 公开了一种差分放大器电路，其中电阻器（89,91）和电容器（90,92）分别连接在差分对NMOS晶体管（85,87）和电源（2）的源极之间。 电阻器（89,91）提高NMOS晶体管的源极电位，以在不产生从差分放大器电路输出的信号电平的转变的时间内减小电流流动，从而降低差分放大器电路中的功耗。 电容器（90,92）在信号电平转换期间减轻电阻器（89,91）的电压降的影响，以防止差分放大器电路的工作速度降低。

    Semiconductor memory device that can carry out read disturb testing and burn-in testing reliably
    73.
    发明授权
    Semiconductor memory device that can carry out read disturb testing and burn-in testing reliably 失效
    可以可靠地进行读取干扰测试和老化测试的半导体存储器件

    公开(公告)号：US5917766A

    公开(公告)日：1999-06-29

    申请号：US978594

    申请日：1997-11-26

    申请人： Takaharu Tsuji ,  Mikio Asakura ,  Tadaaki Yamauchi ,  Koji Tanaka

    发明人： Takaharu Tsuji ,  Mikio Asakura ,  Tadaaki Yamauchi ,  Koji Tanaka

    IPC分类号： G11C29/34 ,  G11C29/50 ,  G11C7/00

    CPC分类号： G11C29/34 ,  G11C29/50 ,  G11C11/401

    摘要： A semiconductor memory device that operates in various modes such as in a normal operation mode and a disturb accelerated test mode in which two word lines are activated simultaneously, includes a boosting power supply circuit, a boosted voltage supply line, and an input terminal connected to the boosted voltage supply line. In a disturb accelerated test mode or in a burn-in test mode, an external voltage is supplied from an external power supply to the input terminal. A word line is reliably boosted in voltage in a disturb accelerated test mode.

    摘要翻译： 一种半导体存储器件，其工作在诸如正常操作模式和同时激活两个字线的干扰加速测试模式的各种模式中，包括升压电源电路，升压电源线​​和连接到 升压电源线​​。 在干扰加速测试模式或老化测试模式下，外部电源从外部电源提供给输入端。 在干扰加速测试模式下，字线可靠地升高电压。

    Synchronous semiconductor memory device operating in synchronization with external clock signal
    74.
    发明授权
    Synchronous semiconductor memory device operating in synchronization with external clock signal 失效
    同步半导体存储器件与外部时钟信号同步工作

    公开(公告)号：US5691955A

    公开(公告)日：1997-11-25

    申请号：US652048

    申请日：1996-05-23

    申请人： Tadaaki Yamauchi

    发明人： Tadaaki Yamauchi

    IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C11/41 ,  G11C7/00

    CPC分类号： G11C7/1018

    摘要： A synchronous semiconductor memory device according to the present invention is provided with two column address counters corresponding to two banks. The two column address counters receives two reference internal column address signals output from the two column address buffers. Each of the column address counters outputs internal column address signals successively and alternately according to the reference internal column address signals. As a result, when the access is to be performed alternately to the two banks, it would not be necessary to input an external column address signal each time the bank to be accessed changes, so that it is made possible to simplify the address input.

    摘要翻译： 根据本发明的同步半导体存储器件具有对应于两个存储体的两列地址计数器。 两列地址计数器接收从两列地址缓冲器输出的两个参考内部列地址信号。 每个列地址计数器根据参考内部列地址信号连续交替地输出内部列地址信号。 结果，当要对两个存储体交替执行访问时，每当要访问的存储体改变时，不需要输入外部列地址信号，使得可以简化地址输入。

    SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY BLOCK CONFIGURATION
    75.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY BLOCK CONFIGURATION 失效
    具有存储块配置的半导体存储器件

    公开(公告)号：US20120230107A1

    公开(公告)日：2012-09-13

    申请号：US13481540

    申请日：2012-05-25

    申请人： Taku Ogura ,  Tadaaki Yamauchi ,  Hidenori Mitani ,  Takashi Kubo ,  Kengo Aritomi

    发明人： Taku Ogura ,  Tadaaki Yamauchi ,  Hidenori Mitani ,  Takashi Kubo ,  Kengo Aritomi

    IPC分类号： G11C16/04

    CPC分类号： G11C29/50 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/02 ,  G11C29/025 ,  G11C29/12005 ,  G11C29/80 ,  G11C29/82 ,  G11C29/832 ,  G11C2029/1202 ,  G11C2029/4402 ,  G11C2029/5006

    摘要： A semiconductor device includes a semiconductor substrate having first and second edge lines, address pads along the first edge line, and memory mats, each including normal memory blocks and a spare memory block. Each normal memory block has nonvolatile memory cells and is a unit of batch erase. The memory mats are arranged in a U-shaped area having a hollow portion facing the second edge line. The device includes column decoders arranged correspondingly to the memory mats, an analog/logic circuit arranged in the hollow portion, and a power supply pad arranged between the analog/logic circuit and the second edge line. The analog/logic circuit includes a charge pump circuit. The device further includes a first power supply interconnection supplying power supply voltage to the charge pump circuit from the power supply pad, and a second power supply interconnection supplying power supply voltage to the column decoder from the power supply pad.

    摘要翻译： 半导体器件包括具有第一和第二边缘线的半导体衬底，沿着第一边缘线的地址焊盘和存储器衬垫，每个存储器衬垫都包括正常存储器块和备用存储块。 每个正常的存储器块都具有非易失性存储器单元，并且是批量擦除的单元。 存储垫被布置在具有面向第二边缘线的中空部分的U形区域中。 该设备包括对应于存储器垫布置的列解码器，布置在中空部分中的模拟/逻辑电路以及布置在模拟/逻辑电路和第二边缘线之间的电源焊盘。 模拟/逻辑电路包括电荷泵电路。 该设备还包括从电源焊盘向电荷泵电路供应电源电压的第一电源互连和从电源焊盘向列解码器供电电源电压的第二电源互连。

    Semiconductor memory device
    78.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07466592B2

    公开(公告)日：2008-12-16

    申请号：US11892055

    申请日：2007-08-20

    申请人： Hidenori Mitani ,  Tadaaki Yamauchi ,  Taku Ogura

    发明人： Hidenori Mitani ,  Tadaaki Yamauchi ,  Taku Ogura

    IPC分类号： G11C16/28 ,  G11C16/26 ,  G11C7/14 ,  G11C7/06

    CPC分类号： G11C8/10 ,  G11C7/1006 ,  G11C11/56 ,  G11C2211/5641

    摘要： A multi-level semiconductor memory device for storing multi-level data having three or more values is implemented by utilizing a nonvolatile memory device for storing 2-valued data. Identification of successive 16-bit data externally applied is performed with external address bit AA [2], and a storage block is selected with external address bit AA [23]. Upper word data LW and lower word data UW are compressed into byte data of 8 bits, respectively, and stored in a memory cell array.

    摘要翻译： 通过利用用于存储2值数据的非易失性存储器件来实现用于存储具有三个或更多个值的多电平数据的多电平半导体存储器件。 使用外部地址位AA [2]执行外部施加的连续16位数据的识别，并且使用外部地址位AA [23]选择存储块。 高字数据LW和下字数据UW被分别压缩成8位的字节数据，并存储在存储单元阵列中。

    Semiconductor device with pump circuit
    79.
    发明授权
    Semiconductor device with pump circuit 有权
    带泵电路的半导体器件

    公开(公告)号：US07365578B2

    公开(公告)日：2008-04-29

    申请号：US11822184

    申请日：2007-07-03

    申请人： Minoru Senda ,  Kiyohiro Furutani ,  Taku Ogura ,  Shigehiro Kuge ,  Satoshi Kawasaki ,  Tadaaki Yamauchi

    发明人： Minoru Senda ,  Kiyohiro Furutani ,  Taku Ogura ,  Shigehiro Kuge ,  Satoshi Kawasaki ,  Tadaaki Yamauchi

    IPC分类号： H03K3/00

    CPC分类号： G11C16/30 ,  G11C5/145 ,  G11C16/04 ,  H02M3/073 ,  H02M2003/071 ,  H02M2003/075 ,  H02M2003/077 ,  H03K3/356113

    摘要： In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of −9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.

    摘要翻译： 在本半导体器件中，正的驱动泵电路由外部电源电位EXVDD（例如1.8V）驱动以产生正电压VPC（例如2.4V）。 用于内部操作的负泵电路由正电压VPC驱动以产生对于字线的擦除或类似的内部操作所需的负电压VNA（例如-9.2V）。 用于内部操作的负泵电路可以具有较少数量的泵级，并且因此消耗比通过外部电源电压EXVDD（例如1.8V）驱动电路时更小的面积。