公开(公告)号：US12021045B2

公开(公告)日：2024-06-25

申请号：US18186348

申请日：2023-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Po-Yao Chuang ,  Ming-Chih Yew ,  Shin-Puu Jeng

IPC: H01L23/66 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01Q1/22 ,  H01Q9/04 ,  H01Q9/28 ,  H01Q21/06

CPC classification number: H01L23/66 ,  H01L21/566 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5383 ,  H01L24/09 ,  H01L24/17 ,  H01Q1/2283 ,  H01Q9/045 ,  H01Q9/285 ,  H01Q21/062 ,  H01Q21/065 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2223/6677 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.

公开(公告)号：US11854955B2

公开(公告)日：2023-12-26

申请号：US17383953

申请日：2021-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Meng-Wei Chou ,  Meng-Liang Lin ,  Po-Yao Chuang ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L24/09 ,  H01L2224/02379 ,  H01L2924/3511

Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.

公开(公告)号：US20230387100A1

公开(公告)日：2023-11-30

申请号：US18446291

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yi Yang ,  Po-Yao Chuang ,  Shin-Puu Jeng

IPC: H01L25/18 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5383 ,  H01L25/165 ,  H01L25/50 ,  H01L21/6835

Abstract: A method includes forming a redistribution structure including metallization patterns; attaching a semiconductor device to a first side of the redistribution structure; encapsulating the semiconductor device with a first encapsulant; forming openings in the first encapsulant, the openings exposing a metallization pattern of the redistribution structure; forming a conductive material in the openings, comprising at least partially filling the openings with a conductive paste; after forming the conductive material, attaching integrated devices to a second side of the redistribution structure; encapsulating the integrated devices with a second encapsulant; and after encapsulating the integrated devices, forming a pre-solder material on the conductive material.

公开(公告)号：US20230253301A1

公开(公告)日：2023-08-10

申请号：US18302112

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Po-Yao Chuang ,  Shin-Puu Jeng ,  Techi Wong

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/683

CPC classification number: H01L23/49822 ,  H01L21/561 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L21/486 ,  H01L24/96 ,  H01L21/568 ,  H01L25/0657 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49894 ,  H01L25/50 ,  H01L24/81 ,  H01L24/19 ,  H01L23/3128 ,  H01L21/6835 ,  H01L21/56 ,  H01L2224/02331 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2924/181 ,  H01L2221/68372 ,  H01L2224/18 ,  H01L2924/18161 ,  H01L2221/68359

Abstract: A semiconductor device and method of manufacture are provided whereby an interposer and a first semiconductor device are placed onto a carrier substrate and encapsulated. The interposer comprises a first portion and conductive pillars extending away from the first portion. A redistribution layer located on a first side of the encapsulant electrically connects the conductive pillars to the first semiconductor device.

公开(公告)号：US20220359421A1

公开(公告)日：2022-11-10

申请号：US17870338

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yao Chuang ,  Meng-Wei Chou ,  Shin-Puu Jeng

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

Abstract: Semiconductor devices and method of manufacture are provided. In embodiments a conductive connector is utilized to provide an electrical connection between a substrate and an overlying shield. The conductive connector is placed on the substrate and encapsulated with an encapsulant. Once encapsulated, an opening is formed through the encapsulant to expose a portion of the conductive connector. The shield is deposited through the encapsulant to make an electrical connection to the conductive connector.

公开(公告)号：US20220359410A1

公开(公告)日：2022-11-10

申请号：US17873387

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Po-Yao Chuang ,  Shuo-Mao Chen ,  Feng-Cheng Hsu

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

Abstract: Semiconductor devices and methods of manufacture are provided wherein multiple integrated passive devices are integrated together utilizing an integrated fan out process in order to form a larger device with a smaller footprint. In particular embodiments the multiple integrated passive devices are capacitors which, once stacked together, can be utilized to provide a larger overall capacitance than any single passive device can obtain with a similar footprint.

公开(公告)号：US11302650B2

公开(公告)日：2022-04-12

申请号：US16921907

申请日：2020-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Shin-Puu Jeng ,  Shih-Ting Hung ,  Po-Yao Chuang

IPC: H01L23/552 ,  H01L23/538 ,  H01L25/16 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48

Abstract: A package structure includes a redistribution structure, a first semiconductor die, a first passive component, a second semiconductor die, a first insulating encapsulant, a second insulating encapsulant, a second passive component and a global shielding structure. The redistribution structure includes dielectric layers and conductive layers alternately stacked. The first semiconductor die, the first passive component and the second semiconductor die are disposed on a first surface of the redistribution structure. The first insulating encapsulant is encapsulating the first semiconductor die and the first passive component. The second insulating encapsulant is encapsulating the second semiconductor die, wherein the second insulating encapsulant is separated from the first insulating encapsulant. The second passive component is disposed on a second surface of the redistribution structure. The global shielding structure is surrounding the first insulating encapsulant, the second insulating encapsulant, and covering sidewalls of the redistribution structure.

公开(公告)号：US11296065B2

公开(公告)日：2022-04-05

申请号：US16901682

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Techi Wong ,  Po-Yao Chuang ,  Shuo-Mao Chen ,  Meng-Wei Chou

IPC: H01L23/02 ,  H01L25/18 ,  H01L27/01 ,  H01L23/31 ,  H01L25/065 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/538

Abstract: An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.

公开(公告)号：US11270975B2

公开(公告)日：2022-03-08

申请号：US16934861

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Po-Yao Chuang ,  Shuo-Mao Chen

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L21/56 ,  H01L25/00

Abstract: An embodiment is a structure including a first semiconductor device and a second semiconductor device, a first set of conductive connectors mechanically and electrically bonding the first semiconductor device and the second semiconductor device, a first underfill between the first and second semiconductor devices and surrounding the first set of conductive connectors, a first encapsulant on at least sidewalls of the first and second semiconductor devices and the first underfill, and a second set of conductive connectors electrically coupled to the first semiconductor device, the second set of conductive connectors being on an opposite side of the first semiconductor device as the first set of conductive connectors.

公开(公告)号：US20210343665A1

公开(公告)日：2021-11-04

申请号：US17372677

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yao Chuang ,  Po-Hao Tsai ,  Shin-Puu Jeng

IPC: H01L23/66 ,  H01L21/48 ,  H01L25/065 ,  H01L21/56 ,  H01Q1/22 ,  H01L23/498 ,  H01L23/367

Abstract: A semiconductor device and manufacturing process are provided wherein a first semiconductor device is electrically connected to redistribution structures. An antenna structure is located on an opposite side of the first semiconductor device from the redistribution structures, and electrical connections separate from the first semiconductor device connect the antenna structure to the redistribution structures.