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公开(公告)号：US20220270682A1
公开(公告)日：2022-08-25
申请号：US17743480
申请日：2022-05-13
发明人： Carlos H. Diaz , Hung-Li Chiang , Tzu-Chiang Chen , Yih Wang
摘要： A read method and a write method for a memory circuit are provided, wherein the memory circuit includes a memory cell and a selector electrically coupled to the memory cell. The read method includes applying a first voltage to the selector, wherein a first voltage level of the first voltage is larger than a voltage threshold corresponding to the selector; and applying, after the applying of the first voltage, a second voltage to the selector to sense one or more bit values stored in the memory cell, wherein a second voltage level of the second voltage is constant and smaller than the voltage threshold, wherein a first duration of the applying of the first voltage is smaller than a second duration of the applying of the second voltage, wherein the second voltage is applied following the end of the first duration.
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公开(公告)号：US20220173250A1
公开(公告)日：2022-06-02
申请号：US17674061
申请日：2022-02-17
IPC分类号： H01L29/78 , H01L27/088 , H01L29/66
摘要： An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.
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公开(公告)号：US20220165320A1
公开(公告)日：2022-05-26
申请号：US17103914
申请日：2020-11-24
发明人： Hung-Li Chiang , Chung-Te Lin , Shy-Jay Lin , Tzu-Chiang Chen , Ming-Yuan Song , Hon-Sum Philip Wong
摘要： A memory device and a memory circuit is provided. The memory device includes a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ), a read word line, a selector and a write word line. The MTJ stands on the SOT layer. The read word line is electrically connected to the MTJ. The write word line is connected to the SOT layer through the selector. The write word line is electrically connected to the SOT layer when the selector is turned on, and the write word line is electrically isolated from the SOT layer when the selector is in an off state.
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公开(公告)号：US20220076741A1
公开(公告)日：2022-03-10
申请号：US17529261
申请日：2021-11-18
摘要： A memory device that includes at least one memory cell is introduced. Each of the at least one memory cell is coupled to a bit line and a word line. Each of the at least one memory cell includes a memory element and a selector element, in which the memory element is configured to store data of the at least one memory cell. The selector element is coupled to the memory element in series and is configured to select the memory element for a read operation and amplify the data stored in the memory element in the read operation.
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公开(公告)号：US10418363B2
公开(公告)日：2019-09-17
申请号：US16195162
申请日：2018-11-19
发明人： Hung-Li Chiang , Cheng-Yi Peng , Tsung-Yao Wen , Yee-Chia Yeo , Yen-Ming Chen
IPC分类号： H01L27/092 , H01L29/66 , H01L29/78 , H01L21/3105 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L29/06 , H01L29/08
摘要： A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin.
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公开(公告)号：US20180090570A1
公开(公告)日：2018-03-29
申请号：US15817601
申请日：2017-11-20
发明人： Cheng-Yi Peng , Hung-Li Chiang , Yu-Lin Yang , Chih Chieh Yeh , Yee-Chia Yeo , Chi-Wen Liu
IPC分类号： H01L29/06 , H01L29/775 , H01L29/66 , H01L29/423 , H01L21/306 , H01L27/092 , H01L21/84 , H01L21/8238 , H01L27/12
CPC分类号： H01L29/0673 , H01L21/30604 , H01L21/3065 , H01L21/3081 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/0649 , H01L29/42392 , H01L29/66439 , H01L29/66772 , H01L29/66795 , H01L29/775 , H01L29/78696
摘要： Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
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公开(公告)号：US20150179454A1
公开(公告)日：2015-06-25
申请号：US14579774
申请日：2014-12-22
发明人： Tsung-Lin Lee , Feng Yuan , Hung-Li Chiang , Chih Chieh Yeh
IPC分类号： H01L21/265 , H01L21/324 , H01L29/10 , H01L29/66
CPC分类号： H01L21/265 , H01L21/26506 , H01L21/2654 , H01L21/2658 , H01L21/26586 , H01L21/324 , H01L29/1054 , H01L29/66545 , H01L29/66795 , H01L29/7847
摘要： A method of fabricating a semiconductor device includes providing a substrate having a fin disposed thereon. A gate structure is formed on the fin. The gate structure interfaces at least two sides of the fin. A stress film is formed on the substrate including on the fin. The substrate including the stress film is annealed. The annealing provides a tensile strain in a channel region of the fin. For example, a compressive strain in the stress film may be transferred to form a tensile stress in the channel region of the fin.
摘要翻译： 制造半导体器件的方法包括提供其上布置有翅片的衬底。 在翅片上形成栅极结构。 栅极结构与翅片的至少两侧相接。 在包括翅片的基板上形成应力膜。 将包括应力膜的基板退火。 退火在翅片的通道区域中提供拉伸应变。 例如，应力膜中的压缩应变可能被转移以在翅片的通道区域中形成拉伸应力。
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公开(公告)号：US20240324228A1
公开(公告)日：2024-09-26
申请号：US18679408
申请日：2024-05-30
IPC分类号： H10B43/35 , H01L29/08 , H01L29/165 , H01L29/66 , H01L29/78 , H01L29/792
CPC分类号： H10B43/35 , H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/66795 , H01L29/66833 , H01L29/7848 , H01L29/7851 , H01L29/792
摘要： A memory array and a structure of the memory array are provided. The memory array includes flash transistors, word lines and bit lines. The flash transistors are arranged in columns and rows. The flash transistors in each column are in serial connection with one another. The word lines are respectively coupled to gate terminals of a row of the flash transistors. The bit lines are respectively coupled to opposite ends of a column of the flash transistors. Band-to-band tunneling current at a selected flash transistor is utilized as read current during a read operation. The BTB tunneling current flows from one of the source/drain terminals of the selected flash transistor to the substrate, rather than flowing from one of the source/drain terminals to the other. As a result, charges stored in multiple programming sites of each flash transistor can be respectively sensed.
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公开(公告)号：US20240257866A1
公开(公告)日：2024-08-01
申请号：US18103664
申请日：2023-01-31
发明人： Hung-Li Chiang , Jen-Chieh Liu , Jui-Jen Wu , Meng-Fan Chang , Jer-FU Wang , Iuliana Radu
IPC分类号： G11C11/419 , G11C11/412 , H01L23/528 , H10B10/00
CPC分类号： G11C11/419 , G11C11/412 , H01L23/5283 , H10B10/125
摘要： A semiconductor device includes a memory cell including a first transistor, a second transistor, and a third transistor. The first transistor has a first gate terminal and the second transistor has a second gate terminal, the first gate terminal and the second gate terminal being connected to a first word line and a second word line, respectively. The first transistor has a pair of first source/drain terminals and the second transistor has a pair of second source/drain terminals, one of the pair of first source/drain terminals and one of the pair of second source/drain terminals being connected to a common bit line. The third transistor has a third gate terminal connected to the other of the pair of first source/drain terminals, and a pair of third source/drain terminals connected to the other of the pair of second source/drain terminals and a supply voltage, respectively.
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公开(公告)号：US12040400B2
公开(公告)日：2024-07-16
申请号：US17866803
申请日：2022-07-18
IPC分类号： H01L29/78 , H01L21/8234 , H01L29/06 , H01L29/417 , H01L29/66
CPC分类号： H01L29/785 , H01L21/823431 , H01L29/0665 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a first nanostructure, a second nanostructure, a metal gate stack, and a spacer structure. The first nanostructure is between the second nanostructure and the substrate, the metal gate stack surrounds the first nanostructure and the second nanostructure, and the spacer structure surrounds an upper portion of the metal gate stack over the second nanostructure. The method includes removing the upper portion of the metal gate stack to form a first trench in the spacer structure. The method includes removing a first portion of the second nanostructure through the first trench after removing the upper portion of the metal gate stack.
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