公开(公告)号：US07586130B2

公开(公告)日：2009-09-08

申请号：US11344574

申请日：2006-02-01

申请人： Takahiro Kawashima ,  Tohru Saitoh ,  Takeshi Takagi

发明人： Takahiro Kawashima ,  Tohru Saitoh ,  Takeshi Takagi

IPC分类号： H01L29/732

CPC分类号： H01L29/78696 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1606 ,  H01L29/42384 ,  H01L29/7781 ,  H01L29/78642 ,  Y10S977/938

摘要： A vertical field effect transistor includes: an active region with a bundle of linear structures functioning as a channel region; a lower electrode, functioning as one of source and drain regions; an upper electrode, functioning as the other of the source and drain regions; a gate electrode for controlling the electric conductivity of at least a portion of the bundle of linear structures included in the active region; and a gate insulating film arranged between the active region and the gate electrode to electrically isolate the gate electrode from the bundle of linear structures. The transistor further includes a dielectric portion between the upper and lower electrodes. The upper electrode is located over the lower electrode with the dielectric portion interposed and includes an overhanging portion sticking out laterally from over the dielectric portion. The active region is located right under the overhanging portion of the upper electrode.

摘要翻译： 垂直场效应晶体管包括：具有用作沟道区的线性结构束的有源区; 用作源极和漏极区之一的下电极; 上电极，用作源极和漏极区域中的另一个; 用于控制所述有源区域中包括的所述线性结构束的至少一部分的电导率的栅电极; 以及栅极绝缘膜，其布置在所述有源区和所述栅电极之间，以将所述栅电极与所述线结构的束电隔离。 晶体管还包括在上电极和下电极之间的电介质部分。 上电极位于下电极的上方，电介质部分插入，并且包括从电介质部分的上方横向突出的突出部分。 有源区域位于上电极的伸出部分正下方。

公开(公告)号：US07564073B2

公开(公告)日：2009-07-21

申请号：US11294566

申请日：2005-12-06

申请人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

发明人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC分类号： H01L27/04

CPC分类号： H01L21/823807

摘要： A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.

摘要翻译： 根据本发明的半导体集成电路制造方法包括：通过器件隔离来围绕每个区域来在半导体衬底的表面层部分中形成一对第一器件形成区域和一对第二器件形成区域的步骤; 在前述步骤之后形成覆盖半导体衬底的表面的第一氧化物膜的步骤; 去除所述第一氧化物膜的预期部分以暴露所述一对第二器件形成区域的步骤; 通过选择性外延生长形成一对异质结结构在由此露出的一对第二器件形成区上的步骤; 在上述步骤之后形成覆盖基板表面的第二氧化膜的步骤; 以及在所述一对第一器件形成区域和所述一对第二器件形成区域中的每一个上形成一对栅电极的步骤，由此在所述一对第一器件形成区域中最终形成正常互补MOS晶体管和异质结互补MOS晶体管 形成区域和一对第二装置形成区域。

公开(公告)号：US20070052041A1

公开(公告)日：2007-03-08

申请号：US10558671

申请日：2004-05-31

申请人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Yoshihiko Kanzawa ,  Kouji Katayama ,  Junko Iwanaga

发明人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Yoshihiko Kanzawa ,  Kouji Katayama ,  Junko Iwanaga

IPC分类号： H01L29/94

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/78687

摘要： A semiconductor device according to this invention includes: a first insulating layer (11); a first body section (13) including an island-shaped semiconductor formed on the first insulating layer; a second body section (14) including an island-shaped semiconductor formed on the first insulating layer; a ridge-shaped connecting section (15) formed on the first insulating layer to interconnect the first body section and the second body section; a channel region (15a) formed by at least a part of the connecting section in lengthwise direction of the connecting section; a gate electrode (18) formed to cover a periphery of the channel region, with a second insulating layer intervening therebetween; a source region formed to extend over the first body section and a portion of the connecting section between the first body section and the channel region; and a drain region formed to extend over the second body section and a portion of the connecting section between the second body section and the channel region, wherein a semiconductor forming the channel region has a lattice strain.

摘要翻译： 根据本发明的半导体器件包括：第一绝缘层（11）; 第一主体部分（13），其包括形成在所述第一绝缘层上的岛状半导体; 包括形成在所述第一绝缘层上的岛状半导体的第二主体部分（14） 形成在第一绝缘层上以互连第一主体部分和第二主体部分的脊形连接部分（15）; 由所述连接部的至少一部分在所述连接部的长度方向上形成的通路区域（15a） 形成为覆盖沟道区域的周边的栅极电极（18），其间插入有第二绝缘层; 形成为在第一主体部分上延伸的源极区域和在第一主体部分和沟道区域之间的连接部分的一部分; 以及形成为在第二主体部分上延伸的漏极区域和在第二主体部分和沟道区域之间的连接部分的一部分，其中形成沟道区域的半导体具有晶格应变。

公开(公告)号：US07084026B2

公开(公告)日：2006-08-01

申请号：US10913383

申请日：2004-08-09

申请人： Takeshi Takagi ,  Akira Inoue

发明人： Takeshi Takagi ,  Akira Inoue

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/802 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/78687

摘要： A region of an Si layer 15 located between source and drain regions 19 and 20 is an Si body region 21 which contains an n-type impurity of high concentration. An Si layer 16 and an SiGe layer 17 are, in an as grown state, undoped layers into which no n-type impurity is doped. Regions of the Si layer 16 and the SiGe layer 17 located between the source and drain regions 19 and 20 are an Si buffer region 22 and an SiGe channel region 23, respectively, which contain the n-type impurity of low concentration. A region of an Si film 18 located directly under a gate insulating film 12 is an Si cap region 24 into which a p-type impurity (5×1017 atoms·cm−3) is doped. Accordingly, a semiconductor device in which an increase in threshold voltage is suppressed can be achieved.

摘要翻译： 位于源区和漏区19和20之间的Si层15的区域是含有高浓度的n型杂质的Si体区21。 处于生长状态的Si层16和SiGe层17未掺杂n型杂质的未掺杂层。 位于源区和漏区19和20之间的Si层16和SiGe层17的区域分别是含有低浓度的n型杂质的Si缓冲区22和SiGe沟道区23。 位于栅极绝缘膜12正下方的Si膜18的区域是Si帽区域24，其中p型杂质（5×10 17原子％-3重量％ ）掺杂。 因此，可以实现抑制阈值电压增加的半导体装置。

公开(公告)号：US20060054944A1

公开(公告)日：2006-03-16

申请号：US11260197

申请日：2005-10-28

申请人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Akira Inoue

发明人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Akira Inoue

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/78696 ,  H01L21/76264 ,  H01L21/76281 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/78687 ,  Y10S438/933 ,  Y10S438/938

摘要： The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3), the gate insulation film (10) and the gate electrode (11); wherein the first insulation film (13) overlies a part of the gate insulation film (10) surface. According to the semiconductor device, leakage current at the isolation edge can be suppressed and thus reliability can be improved.

摘要翻译： 本发明提供一种半导体器件，包括：半导体层（3）; 经由栅极绝缘膜（10）形成在所述半导体层（3）上的栅电极（11）; 以及形成在所述半导体层（3），所述栅极绝缘膜（10）和所述栅电极（11）的侧壁的一个或多个的第一绝缘膜（13）。 其中所述第一绝缘膜（13）覆盖所述栅极绝缘膜（10）表面的一部分。 根据半导体装置，可以抑制隔离边缘处的漏电流，从而可以提高可靠性。

公开(公告)号：US20050093020A1

公开(公告)日：2005-05-05

申请号：US10983610

申请日：2004-11-09

申请人： Akira Inoue ,  Takeshi Takagi ,  Yoshihiro Hara ,  Minoru Kubo

发明人： Akira Inoue ,  Takeshi Takagi ,  Yoshihiro Hara ,  Minoru Kubo

IPC分类号： H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/77 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/84 ,  H01L27/092 ,  H01L27/115 ,  H01L27/12 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L29/80 ,  H01L31/0392

CPC分类号： H01L29/802 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/10873 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1222 ,  H01L28/55 ,  H01L29/1054 ,  H01L29/783 ,  H01L29/78687

摘要： A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate 101.

摘要翻译： 依次沉积硅衬底101上的氧化硅膜102，Pt膜103x，Ti膜104x和PZT膜105x。 将Si衬底101放置在室106中，使得PZT膜105x被EHF波108照射。 用EHF波照射局部加热电介质膜，例如PZT膜。 结果，可以改善例如电介质膜的泄漏特性，而不会对形成在Si衬底101上的器件产生不利影响。

公开(公告)号：US06858454B1

公开(公告)日：2005-02-22

申请号：US10674523

申请日：2003-10-01

申请人： Yoshihiko Kanzawa ,  Tohru Saitoh ,  Takeshi Takagi ,  Katsuya Nozawa

发明人： Yoshihiko Kanzawa ,  Tohru Saitoh ,  Takeshi Takagi ,  Katsuya Nozawa

IPC分类号： G01N21/21 ,  G01N21/35 ,  H01L21/66

CPC分类号： G01N21/3563 ,  G01N21/211

摘要： A method for measuring semiconductor constituent element content utilizes the steps of: obtaining a film thickness of an SiGeC layer formed on a semiconductor substrate by evaluation using spectroscopic ellipsometry; measuring infrared absorption spectrum of the SiGeC layer; and obtaining a C content of the SiGeC layer based on the film thickness and the infrared absorption spectrum of the SiGeC layer. The method: obtaining an apparent Ge content of the SiGeC layer by evaluation using spectroscopic ellipsometry; and obtaining an actual Ge content of the SiGeC layer based on the apparent Ge content and the C content. The constituent element content of the SiGeC layer can be easily and accurately measured according to the above-mentioned method.

摘要翻译： 一种测量半导体构成元件含量的方法采用以下步骤：通过使用分光椭圆偏光度法评估在半导体衬底上形成的SiGeC层的膜厚度; 测量SiGeC层的红外吸收光谱; 并根据SiGeC层的膜厚和红外吸收光谱获得SiGeC层的C含量。 该方法：通过使用分光椭偏仪评估获得SiGeC层的表观Ge含量; 并且基于表观Ge含量和C含量获得SiGeC层的实际Ge含量。 根据上述方法可以容易且精确地测量SiGeC层的构成元素含量。

公开(公告)号：US06821870B2

公开(公告)日：2004-11-23

申请号：US10224468

申请日：2002-08-21

申请人： Takeshi Takagi ,  Koichiro Yuki ,  Kenji Toyoda ,  Yoshihiko Kanzawa

发明人： Takeshi Takagi ,  Koichiro Yuki ,  Kenji Toyoda ,  Yoshihiko Kanzawa

IPC分类号： H01L2122

CPC分类号： H01L29/7378 ,  H01L29/161 ,  H01L29/66242

摘要： A heterojunction bipolar transistor is fabricated by stacking a Si collector layer, a SiGeC base layer and a Si emitter layer in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap can be narrower than the band gap of the conventional practical SiGe (the Ge content is about 10%), and good crystalline can be maintained after a heat treatment. As a result, a narrow band gap base with no practical inconvenience can be realized.

摘要翻译： 通过依次堆叠Si集电极层，SiGeC基极层和Si发射极层来制造异质结双极晶体管。 通过使Si集电体层的SiGeC基底层的晶格应变量为1.0％以下，带隙可以窄于现有实际SiGe的带隙（Ge含量为10％左右），良好 结晶可以在热处理后保持。 结果，可以实现没有实际麻烦的窄带隙基。

公开(公告)号：US06821856B2

公开(公告)日：2004-11-23

申请号：US10188108

申请日：2002-07-03

申请人： Takeshi Takagi

发明人： Takeshi Takagi

IPC分类号： H01L21336

CPC分类号： H01L29/66651 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/41725 ,  H01L29/458 ,  H01L29/665 ,  H01L29/783 ,  H01L29/78615 ,  H01L29/78618 ,  H01L29/78639

摘要： A semiconductor device comprises an Si substrate, an isolation insulating film formed on the Si substrate, an Si layer formed on the Si substrate, a gate oxide film formed on the Si layer, a gate electrode formed on the gate oxide film, a sidewall formed on the side face of the gate electrode, a gate silicide film formed on the gate electrode, source and drain regions formed at both the sides of the gate electrode and including a part of the Si layer, and a silicide film formed on the source and drain regions. Because the source and drain regions are formed on a layer-insulating film so as to be overlayed, it is possible to decrease the active region and cell area of a device. Thereby, a high-speed operation and high integration can be realized.

摘要翻译： 半导体器件包括Si衬底，形成在Si衬底上的隔离绝缘膜，形成在Si衬底上的Si层，形成在Si层上的栅极氧化膜，形成在栅氧化膜上的栅电极，形成侧壁 在栅电极的侧面上，形成在栅电极上的栅极硅化物膜，形成在栅电极的两侧的源极和漏极区，并且包括一部分Si层，以及形成在源极上的硅化物膜 漏区。 因为源极和漏极区域形成在层间绝缘膜上以便被覆盖，所以可以减小器件的有源区域和单元面积。 由此，能够实现高速运转，高集成化。

公开(公告)号：US06642607B2

公开(公告)日：2003-11-04

申请号：US10061365

申请日：2002-02-04

申请人： Teruhito Ohnishi ,  Takeshi Takagi ,  Akira Asai ,  Taizo Fujii ,  Mitsuo Sugiura ,  Yoshihisa Minami

发明人： Teruhito Ohnishi ,  Takeshi Takagi ,  Akira Asai ,  Taizo Fujii ,  Mitsuo Sugiura ,  Yoshihisa Minami

IPC分类号： H01L2993

CPC分类号： H01L29/93 ,  H01L27/0664 ,  H01L27/0808

摘要： A variable capacitor includes an N+ layer including a variable capacitance region, a P+ layer epitaxially grown on the N+ layer and formed from a SiGe film and a Si film, and a P-type electrode. An NPN-HBT (Hetero-junction Bipolar Transistor) includes a collector diffusion layer formed simultaneously with the N+ layer of the variable capacitor, a collector layer, and a Si/SiGe layer epitaxially grown simultaneously with the P+ layer of the variable capacitor. Since a depletion layer formed in a PN junction of the variable capacitor can extend entirely across the N+ layer, reduction in variation range of the capacitance can be suppressed.

摘要翻译： 可变电容器包括N +层，包括可变电容区，在N +层上外延生长并由SiGe膜和Si膜形成的P +层和P型电极。 NPN-HBT（异质结双极晶体管）包括与可变电容器的N +层同时形成的集电极扩散层，集电极层和与P +层同时外延生长的Si / SiGe层 的可变电容器。 由于形成在可变电容器的PN结中的耗尽层可以完全延伸穿过N +层，所以可以抑制电容的变化范围的减小。