公开(公告)号：US07268042B2

公开(公告)日：2007-09-11

申请号：US11005015

申请日：2004-12-07

申请人： Digh Hisamoto ,  Kan Yasui

发明人： Digh Hisamoto ,  Kan Yasui

IPC分类号： H01L21/8247

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/66825

摘要： A nonvolatile semiconductor memory device of a split gate structure having a gate of low resistance suitable to the arrangement of a memory cell array is provided. When being formed of a side wall spacer, a memory gate is formed of polycrystal silicon and then replaced with nickel silicide. Thus, its resistance can be lowered with no effect on the silicidation to the selection gate or the diffusion layer.

摘要翻译： 提供了具有适合于存储单元阵列的布置的具有低电阻的栅极的分离栅极结构的非易失性半导体存储器件。 当由侧壁间隔物形成时，存储栅由多晶硅形成，然后被硅化镍替代。 因此，其电阻可以降低，而对选择栅极或扩散层的硅化物没有影响。

公开(公告)号：US20070207581A1

公开(公告)日：2007-09-06

申请号：US11797839

申请日：2007-05-08

申请人： Kan Yasui ,  Digh Hisamoto ,  Shinichiro Kimura

发明人： Kan Yasui ,  Digh Hisamoto ,  Shinichiro Kimura

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4232 ,  H01L29/792

摘要： In a split gate type nonvolatile memory cell in which a MOS transistor for a nonvolatile memory using a charge storing film and a MOS transistor for selecting it are adjacently formed, the charge storing characteristic is improved and the resistance of the gate electrode is reduced. In order to prevent the thickness reduction at the corner portion of the charge storing film and improve the charge storing characteristic, a taper is formed on the sidewall of the select gate electrode. Also, in order to stably perform a silicide process for reducing the resistance of the self-aligned gate electrode, the sidewall of the select gate electrode is recessed. Alternatively, a discontinuity is formed between the upper portion of the self-aligned gate electrode and the upper portion of the select gate electrode.

公开(公告)号：US07259422B1

公开(公告)日：2007-08-21

申请号：US11653832

申请日：2007-01-17

申请人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： H01L29/788

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833

摘要： A memory cell includes a selective gate and a memory gate arranged on one side surface of the selective gate. The memory gate includes one part formed on one side surface of the selective gate and the other part electrically isolated from the selective gate and a p-well through an ONO layer formed below the memory gate. A sidewall-shaped silicon oxide is formed on side surfaces of the selective gate, and a sidewall-shaped silicon dioxide layer and a silicon dioxide layer are formed on side surfaces of the memory gate. The ONO layer formed below the memory gate is terminated below the silicon oxide, and prevents generation of a low breakdown voltage region in the silicon oxide near an end of the memory gate during deposition of the silicon dioxide layer.

摘要翻译： 存储单元包括布置在选择栅极的一个侧表面上的选择栅极和存储栅极。 存储器栅极包括形成在选择栅极的一个侧表面上的一个部分和与选择栅极电隔离的另一部分，以及通过形成在存储栅极下方的ONO层的p阱。 在选择栅极的侧面上形成侧壁状的氧化硅，在存储栅的侧面形成侧壁状的二氧化硅层和二氧化硅层。 形成在存储器栅下方的ONO层终止在氧化硅的下方，并且防止在沉积二氧化硅层期间在存储栅的端部附近的硅氧化物中产生低的击穿电压区域。

公开(公告)号：US07245531B2

公开(公告)日：2007-07-17

申请号：US11198191

申请日：2005-08-08

申请人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

发明人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

IPC分类号： G11C11/34

CPC分类号： H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

摘要： Memory cells are disposed in plural array form. Select gate electrodes of the memory cells arranged in an X direction are connected to one another by select gate lines respectively. Memory gate electrodes are connected by memory gate lines respectively. The memory gate lines respectively connected to the memory gate electrodes of the memory cells adjacent to one another through source regions interposed therebetween are not electrically connected to one another. Each of the select gate lines has a first portion that extends in the X direction, and a second portion 9b of which one end is connected to the first portion and extends in a Y direction. The memory gate line is formed on its corresponding sidewall of the select gate line with an insulating film interposed therebetween. The memory gate line has a contact section that extends in the X direction from over a second portion of the select gate line to over an element isolation region, and is connected to its corresponding wiring through a plug that buries a contact hole formed over the contact section.

摘要翻译： 存储单元以多个阵列形式布置。 选择沿X方向布置的存储单元的选择栅电极分别通过选择栅极线彼此连接。 存储器栅极电极分别由存储器栅极线连接。 分别连接到彼此相邻的存储单元的存储器栅极的存储栅极线通过其间的源极区域彼此不电连接。 每个选择栅极线具有在X方向上延伸的第一部分和其一端连接到第一部分并沿Y方向延伸的第二部分9b。 存储栅极线在其选择栅线的相应侧壁上形成有介于其间的绝缘膜。 存储栅极线具有接触部分，该接触部分在选择栅极线的第二部分上方在X方向上延伸到元件隔离区域上方，并且通过塞子连接到其对应的布线，所述插头埋设形成在触点上的接触孔 部分。

公开(公告)号：US07235441B2

公开(公告)日：2007-06-26

申请号：US10901347

申请日：2004-07-29

申请人： Kan Yasui ,  Digh Hisamoto ,  Shinichiro Kimura

发明人： Kan Yasui ,  Digh Hisamoto ,  Shinichiro Kimura

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4232 ,  H01L29/792

摘要： In a split gate type nonvolatile memory cell in which a MOS transistor for a nonvolatile memory using a charge storing film and a MOS transistor for selecting it are adjacently formed, the charge storing characteristic is improved and the resistance of the gate electrode is reduced. In order to prevent the thickness reduction at the corner portion of the charge storing film and improve the charge storing characteristic, a taper is formed on the sidewall of the select gate electrode. Also, in order to stably perform a silicide process for reducing the resistance of the self-aligned gate electrode, the sidewall of the select gate electrode is recessed. Alternatively, a discontinuity is formed between the upper portion of the self-aligned gate electrode and the upper portion of the select gate electrode.

摘要翻译： 在其中使用电荷存储膜的非易失性存储器的MOS晶体管和用于选择它的MOS晶体管相邻形成的分离栅极型非易失性存储单元中，电荷存储特性得到改善，栅电极的电阻降低。 为了防止电荷存储薄膜的拐角部分的厚度减小并且提高电荷存储特性，在选择栅电极的侧壁上形成锥形。 此外，为了稳定地进行用于降低自对准栅电极的电阻的硅化物工艺，选择栅电极的侧壁凹陷。 或者，在自对准栅电极的上部和选择栅电极的上部之间形成不连续。

公开(公告)号：US20060281262A1

公开(公告)日：2006-12-14

申请号：US11437610

申请日：2006-05-22

申请人： Digh Hisamoto ,  Shin'ichiro Kimura ,  Daiske Okada ,  Kan Yasui

发明人： Digh Hisamoto ,  Shin'ichiro Kimura ,  Daiske Okada ,  Kan Yasui

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L27/115 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/792

摘要： An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times. In the case of conventional nonvolatile semiconductor storage devices having a split-gate structure, there is a tradeoff between the read current and the maximum allowable number of reprogramming operations. To overcome this problem, an integrated semiconductor nonvolatile storage device of the present invention is configured such that memory cells having different memory gate lengths are integrated on the same chip. This allows the device to be read at high speed and reprogrammed an increased number of times.

摘要翻译： 本发明的目的是提供一种可以高速读取并重新编程次数增加的集成半导体非易失性存储装置。 在具有分割栅结构的常规非易失性半导体存储器件的情况下，读取电流和最大可允许重编程操作次数之间存在权衡。 为了克服这个问题，本发明的集成半导体非易失性存储装置被配置为使得具有不同存储器栅极长度的存储单元集成在同一芯片上。 这允许以高速读取设备并重新编程增加的次数。

公开(公告)号：US20060028868A1

公开(公告)日：2006-02-09

申请号：US11198191

申请日：2005-08-08

申请人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

发明人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

IPC分类号： G11C11/34 ,  G11C5/06

CPC分类号： H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

摘要： Memory cells are disposed in plural array form. Select gate electrodes of the memory cells arranged in an X direction are connected to one another by select gate lines respectively. Memory gate electrodes are connected by memory gate lines respectively. The memory gate lines respectively connected to the memory gate electrodes of the memory cells adjacent to one another through source regions interposed therebetween are not electrically connected to one another. Each of the select gate lines has a first portion that extends in the X direction, and a second portion 9b of which one end is connected to the first portion and extends in a Y direction. The memory gate line is formed on its corresponding sidewall of the select gate line with an insulating film interposed therebetween. The memory gate line has a contact section that extends in the X direction from over a second portion of the select gate line to over an element isolation region, and is connected to its corresponding wiring through a plug that buries a contact hole formed over the contact section.

摘要翻译： 存储单元以多个阵列形式布置。 选择沿X方向布置的存储单元的选择栅电极分别通过选择栅极线彼此连接。 存储器栅极电极分别由存储器栅极线连接。 分别连接到彼此相邻的存储单元的存储器栅极的存储栅极线通过其间的源极区域彼此不电连接。 每个选择栅极线具有在X方向上延伸的第一部分和其一端连接到第一部分并沿Y方向延伸的第二部分9b。 存储栅极线在其选择栅线的相应侧壁上形成有介于其间的绝缘膜。 存储栅极线具有接触部分，该接触部分在选择栅极线的第二部分上方在X方向上延伸到元件隔离区域上方，并且通过塞子连接到其对应的布线，所述插头埋设形成在触点上的接触孔 部分。

公开(公告)号：US20050285181A1

公开(公告)日：2005-12-29

申请号：US11147243

申请日：2005-06-08

申请人： Kan Yasui ,  Digh Hisamoto ,  Toshihiro Tanaka ,  Takashi Yamaki

发明人： Kan Yasui ,  Digh Hisamoto ,  Toshihiro Tanaka ,  Takashi Yamaki

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/3418 ,  G11C16/0466 ,  G11C16/3427 ,  H01L27/115 ,  H01L29/4232 ,  H01L29/792

摘要： In a non-volatile semiconductor memory device using a charge storage film, it is intended to prevent a sequence disturb such as an erroneous write or erase of another memory cell on one and same word line which occurs depending on a bias transition path in stand-by state and write state. In connection with rise and fall of a word line bias, the present invention adopts a procedure such that a diffusion region voltage Vs on a memory transistor side is changed, and after the voltage Vs passes a certain intermediate value Vsx, a gate voltage Vmg of the memory transistor is changed. Alternatively, there is adopted a procedure such that the gate voltage Vmg of the memory transistor is changed, and after the voltage Vmg passes a certain intermediate value Vmgx, the diffusion layer voltage Vs on the memory transistor side is changed. The values of Vsx and Vmgx are determined from the magnitude of the electric field in a gate insulating film not causing FN tunneling electron injection that causes a change in threshold voltage and the magnitude of a potential barrier against holes not causing BTBT hot hole injection.

摘要翻译： 在使用电荷存储膜的非易失性半导体存储器件中，旨在防止在根据独立的偏置过渡路径发生的同一字线上的另一个存储单元的错误写入或擦除的序列干扰， 按状态和写状态。 关于字线偏差的上升和下降，本发明采用使存储晶体管侧的扩散区电压Vs变化的过程，在电压Vs经过一定的中间值Vsx之后，栅极电压Vmg为 存储晶体管被改变。 或者，采用使存储晶体管的栅极电压Vmg改变的过程，并且在电压Vmg经过一定的中间值Vmgx之后，存储晶体管侧的扩散层电压Vs被改变。 Vsx和Vmgx的值由栅极绝缘膜中不引起FN隧穿电子注入的电场的大小确定，导致阈值电压的变化以及针对未引起BTBT热空穴注入的孔的势垒的大小。

公开(公告)号：US06723144B2

公开(公告)日：2004-04-20

申请号：US10308088

申请日：2002-12-03

申请人： Souichi Katagiri ,  Kan Yasui ,  Ryousei Kawai ,  Sadayuki Nishimura ,  Masahiko Sato ,  Yoshio Kawamura ,  Shigeo Moriyama

发明人： Souichi Katagiri ,  Kan Yasui ,  Ryousei Kawai ,  Sadayuki Nishimura ,  Masahiko Sato ,  Yoshio Kawamura ,  Shigeo Moriyama

IPC分类号： B24D302

CPC分类号： B24B37/245 ,  B24D3/32 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76819 ,  H01L21/7684

摘要： A film formed on a surface of a wafer on which an integrated circuit is to be constructed can be planarized by using a fixed abrasive tool regardless of the width of elements of a pattern underlying the film. The fixed abrasive tool is liable to form scratches in the surface of the film. A planarizing process of the present invention employs a fixed abrasive tool containing substances harder than the film to be planarized in a content of 10 ppm or below and having a mean pore diameter of 0.2 &mgr;m or below.

摘要翻译： 形成在其上将要构造集成电路的晶片的表面上的膜可以通过使用固定的研磨工具进行平面化，而与薄膜下面的图案的元件的宽度无关。 固定的研磨工具易于在膜表面形成划痕。 本发明的平面化方法使用含有比待平坦化的膜更硬的物质的固定研磨工具，其含量为10ppm以下，平均孔径为0.2μm以下。

公开(公告)号：US6099393A

公开(公告)日：2000-08-08

申请号：US80728

申请日：1998-05-21

申请人： Soichi Katagiri ,  Shigeo Moriyama ,  Kan Yasui ,  Katsuhiko Yamaguchi

发明人： Soichi Katagiri ,  Shigeo Moriyama ,  Kan Yasui ,  Katsuhiko Yamaguchi

IPC分类号： B24B37/00 ,  B24B53/007 ,  B24B53/013 ,  H01L21/304 ,  B24B1/00

CPC分类号： B24B53/017 ,  B24B53/013

摘要： In the polishing machine 10 for pressing the polished surface 7 of the workpiece 1 against the face where there are abrasives 15 of the rotating polishing tool 11 and executing chemical mechanical polishing, the brushing device 30, the cleaner 40, the abrasive supplier 52, and the pure water supplier 60 are sequentially arranged behind the location of the head 20 for pressing the workpiece 1 against the polishing tool 11 in the rotational direction. The cleaner 40 sprays the cleaning water 47 to the face where there are abrasives 15 of the rotating polishing tool 11 and sucks and collects it by the vacuum hole 45. Fresh slurry 62 is always supplied by the slurry supplier 63 comprising the abrasive supplier 52 and the pure water supplier 60.

摘要翻译： 在用于将工件1的抛光表面7压靠在旋转抛光工具11的磨料15的表面上并执行化学机械抛光的抛光机10中，刷洗装置30，清洁器40，磨料供应器52和 纯水供应器60顺序地布置在头部20的位置之后，用于将工件1沿着旋转方向压靠在抛光工具11上。 清洁器40将清洗水47喷射到旋转研磨工具11的磨料15的表面，并通过真空孔45吸收并收集。新鲜浆料62总是由包含磨料供应器52的浆料供给器63供应， 纯水供应商60。