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公开(公告)号：US06880074B2
公开(公告)日：2005-04-12
申请号：US09681077
申请日：2000-12-22
CPC分类号： G06F9/30069 , G06F1/3203 , G06F1/329 , G06F8/4432 , G06F9/30145 , Y02D10/24 , Y02D10/41
摘要： Processor overhead is reduced and processor performance, particularly processing speed and power savings, is improved, allowing real-time processor restarts, by skipping operational codes (opcodes) singly or in groups in accordance with one or more execution bits set during post-processing in opcodes preceding opcodes to be skipped. Thus portions of an application program which consume excessive power or are unsupported in particular operating environments can be easily and selectively de-activate while maintaining the integrity of the applications program. Local or cache memory is also effectively expanded and processor performance improved by eliminating opcodes from local or cache memory which will not be called.
摘要翻译： 通过根据在后处理期间设置的一个或多个执行位单独或分组跳过操作代码（操作码），处理器开销降低，特别是处理速度和功率节省，提高处理器性能，允许实时处理器重新启动 操作码之前的操作码将被跳过。 因此，在保持应用程序的完整性的同时，可以容易地和选择性地去激活在特定操作环境中消耗过多功率或不受支持的应用程序的部分。 还可以通过从本地或高速缓冲存储器中消除不被调用的操作码来有效地扩展本地或高速缓冲存储器并提高处理器性能。
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72.发明授权公开(公告)号：US06794706B2
公开(公告)日：2004-09-21
申请号：US10064493
申请日：2002-07-22
申请人： Fen Chen , Rajarao Jammy , Baozhen Li , Sebastian T. Ventrone
发明人： Fen Chen , Rajarao Jammy , Baozhen Li , Sebastian T. Ventrone
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/0217 , H01L21/022 , H01L21/02326 , H01L21/28194 , H01L21/3144 , H01L28/40 , H01L29/513 , H01L29/518 , H01L29/94
摘要： A capacitor structure having a re-oxide layer on a nitride layer, wherein an interface between the nitride layer and the re-oxide layer includes electron traps. Characteristics of the carrier traps control a voltage output of the device. The thickness of the nitride layer and the re-oxide layer also control the voltage output. The nitride layer and a re-oxide layer form a dielectric capacitor. The dielectric capacitor undergoes a trap filled limit voltage, wherein a consistent voltage is output for a plurality of currents.
摘要翻译： 一种在氮化物层上具有再氧化物层的电容器结构，其中氮化物层和再氧化物层之间的界面包括电子阱。 载波阱的特性控制器件的电压输出。 氮化物层和再氧化物层的厚度也控制电压输出。 氮化物层和再氧化物层形成介质电容器。 介质电容器经历陷阱填充极限电压，其中为多个电流输出一致的电压。
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公开(公告)号：US06678847B1
公开(公告)日：2004-01-13
申请号：US09303211
申请日：1999-04-30
IPC分类号： G01R3128
CPC分类号： G01R31/318555 , G01R31/318538 , G06F9/30116 , G06F11/3648
摘要： A system and method for determining the operational state of a logic device having a plurality of shadow registers, each associated with one of a plurality of functional registers. Data stored in a functional register is, under selected conditions, also stored in an associated shadow register. These conditions include without limitation receipt by the functional register of predetermined event information such as an opcode, memory address or other information. Data in a given set of functional registers, e.g., registers making up pipeline stages in a microprocessor, may be stored in shadow registers simultaneously or sequentially when given data reaches a given register in the set. Additionally, data is stored in the shadow registers without interrupting execution cycles of the logic device.
摘要翻译： 一种用于确定具有多个影子寄存器的逻辑设备的操作状态的系统和方法，每个影子寄存器与多个功能寄存器之一相关联。 存储在功能寄存器中的数据在选定的条件下也存储在相关的影子寄存器中。 这些条件包括但不限于功能寄存器对诸如操作码，存储器地址或其他信息的预定事件信息的接收。 当给定数据到达集合中的给定寄存器时，给定的一组功能寄存器（例如，组成微处理器中的流水线级的寄存器）中的数据可以同时或顺序存储在影子寄存器中。 此外，数据存储在影子寄存器中，而不会中断逻辑器件的执行周期。
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公开(公告)号：US06545521B2
公开(公告)日：2003-04-08
申请号：US09895778
申请日：2001-06-29
IPC分类号： H03L500
CPC分类号： H04L25/0292 , H03K19/00315 , H04L25/0266 , H04L25/0272
摘要： The present invention provides a receiver device having multiple voltage supplies that allows the output stage of the receiver device to go to a safe state whenever its voltage is disconnected or powered-down, independent of any of its normal control circuits. Furthermore, the isolation of the multiple voltage supplies provides a low skew at the output of the receiver device.
摘要翻译： 本发明提供了一种具有多个电压源的接收机设备，每当其电压断开或掉电时，接收机设备的输出级都能够进入安全状态，独立于其任何正常的控制电路。 此外，多个电压源的隔离在接收器件的输出处提供低偏移。
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75.发明授权System and method for AC performance tuning by thereshold voltage shifting in tubbed semiconductor technology 失效通过液晶半导体技术中的阈值电压偏移进行交流性能调谐的系统和方法公开(公告)号：US06487701B1
公开(公告)日：2002-11-26
申请号：US09711744
申请日：2000-11-13
IPC分类号： G06F1750
CPC分类号： G01R31/3163 , G01R31/2891
摘要： A system and method are described for separating the bulk connections for FETs on a semiconductor wafer from the supply rails, testing the wafer to determine if a shift in the threshold voltage, VT, of certain devices within the wafer, as defined by the bulk-wells, can remove an AC defect in the IC circuit, and tailoring the voltage or voltages applied to the bulk nodes, post-manufacture, such that the integrated circuit meets its performance targets or is sorted to a more valuable performance level. The method requires generating a gate level netlist of the IC's circuitry and performing timing calculations on these circuit netlists using static timing analyses, functional delay simulations, circuit activity analyses, and functional performance testing. The failures are then correlated to respective IC circuits, worst case slack circuits are investigated, and proposed changes to the threshold voltages are employed in the hardware.
摘要翻译： 描述了一种系统和方法，用于将半导体晶片上的FET的体连接与电源轨分开，测试晶片以确定晶片内的某些器件的阈值电压VT是否偏移， 孔可以去除IC电路中的AC缺陷，并且定制施加到散装节点的电压或电压，后制造，使得集成电路满足其性能目标或被分类到更有价值的性能水平。 该方法需要生成IC电路的门级网表，并使用静态时序分析，功能延迟模拟，电路活动分析和功能性能测试来对这些电路网表执行定时计算。 然后将故障与相应的IC电路相关联，最坏情况下调查松弛电路，并且在硬件中采用提出的阈值电压的改变。
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76.发明授权Method and circuit for providing copy protection in an application-specific integrated circuit 失效在专用集成电路中提供复制保护的方法和电路公开(公告)号：US06246254B1
公开(公告)日：2001-06-12
申请号：US09455969
申请日：1999-12-06
IPC分类号： H03K19007
CPC分类号： G06F21/76 , G06F21/71 , G06F2221/2137
摘要： A method for preventing illicit copying of an application specific integrated circuit (ASIC). The ASIC is defined by a net list which includes a timer circuit for disabling the ASIC. The timer circuit includes a plurality of stages which are distributed in different cores of the ASIC to inhibit detection and removal of the circuit. The timer times out after a period which is set to permit evaluation of the ASIC design. Following the time out period, further use of the ASIC design is inhibited.
摘要翻译： 一种用于防止专用集成电路（ASIC）的非法复制的方法。 ASIC由包括用于禁用ASIC的定时器电路的网络列表定义。 定时器电路包括分布在ASIC的不同芯中的多个级，以阻止电路的检测和去除。 定时器在设置为允许对ASIC设计进行评估的时间段之后超时。 在超时期后，ASIC设计的进一步使用受到阻碍。
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公开(公告)号：US5902044A
公开(公告)日：1999-05-11
申请号：US883911
申请日：1997-06-27
申请人： Wilbur Pricer , Kenneth Joseph Goodnow , Michel S. Michail , Janak Ghanshyambhai Patel , Sebastian T. Ventrone
发明人： Wilbur Pricer , Kenneth Joseph Goodnow , Michel S. Michail , Janak Ghanshyambhai Patel , Sebastian T. Ventrone
CPC分类号： G01K3/14
摘要： A matrix of thermal sensors is provided for accurately evaluating the thermal characteristics of an integrated circuit. The integrated circuit is evenly divided into a plurality of sectors in which a thermal comparison to a known thermal mass will be performed. Each sector includes at least one dual cell comprising a local thermal sensor for providing an output corresponding to a local temperature of the integrated circuit in that sector, and a background thermal sensor. The outputs of selective ones of the background thermal sensors are combined to provide a signal corresponding to a background temperature of the integrated circuit. A decoder/enabler arrangement is used to selectively gate the output of a specific local thermal sensor in a sector to a difference circuit where it is compared to the collective output of selected ones of the background sensors to generate a thermal measurement of the sector under test.
摘要翻译： 提供了一种热传感器矩阵，用于精确评估集成电路的热特性。 集成电路被均匀地分成多个扇区，其中将对已知的热质量进行热比较。 每个扇区包括至少一个双电池，其包括本地热传感器，用于提供对应于该扇区中的集成电路的局部温度的输出和背景热传感器。 背景热传感器中的选择性传感器的输出被组合以提供对应于集成电路的背景温度的信号。 解码器/使能器布置用于选择性地将扇区中的特定局部热传感器的输出门控到差分电路，其中与所选择的背景传感器的集合输出进行比较以产生被测扇区的热测量 。
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78.发明授权Method and apparatus for switching between clock generators only when activity on a bus can be stopped 失效只有当总线上的活动可以停止时才在时钟发生器之间切换的方法和装置
公开(公告)号：US5594895A
公开(公告)日：1997-01-14
申请号：US430120
申请日：1995-04-27
CPC分类号： G06F1/08 , H04B2215/064 , H04B2215/065
摘要： Method and apparatus for providing a microprocessor with a divide by one frequency generator, while permitting the external clock driving the generator to vary in frequency without interruption of the operations of the microprocessor. A divide by two clock generator is also provided on the microprocessor chip. When a change in the frequency of the external clock is desired a request signal is provided to the chip. After a period of time has elapsed that permits the microprocessor to achieve a "safe" mode in which processing integrity is maintained even if the clock signal is interrupted, the divide by two clock generator is switched into operation. The external clock is then allowed to change frequency after which the divide by one clock generator is reactivated, following a period of time sufficient to allow the divide by one clock generator to stabilize.
摘要翻译： 用于通过一个频率发生器为微处理器提供除法的方法和装置，同时允许外部时钟驱动发生器频率变化而不中断微处理器的操作。 在微处理器芯片上还提供了两个时钟发生器的除法。 当需要外部时钟频率的改变时，向芯片提供请求信号。 在经过一段时间后，即使时钟信号被中断，微处理器也能够实现“安全”模式，即使处理完整性得到保持，两个时钟发生器的除法也被切换成操作。 然后允许外部时钟改变频率，在此之后，一个时钟发生器的除法被重新激活，足以允许一个时钟发生器的除法稳定的时间段。
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79.发明授权Interprocessor communication system for direct processor to processor communication between internal general purpose registers transparent to the execution of processors thereof 失效处理器间通信系统，用于直接处理器与内部通用寄存器之间的处理器通信，对其处理器的执行透明
公开(公告)号：US5440689A
公开(公告)日：1995-08-08
申请号：US161858
申请日：1993-12-03
IPC分类号： G06F13/38 , G06F15/16 , G06F15/17 , G06F15/177
CPC分类号： G06F15/17
摘要： A system for direct interprocessor communication in a multiprocessor data processing environment. The system utilizes conventional direct data transfer means and existing I/O port instruction capabilities available on most microprocessors. A destination processor requiring data from one of a source processor's internal registers generates a unique address which specifies the register containing the required data. The address is sent to the data transfer means, causing the direct transfer of data from the designated source processor internal register to the destination processor. Specific circuitry to accomplish this direct data transfer function is described.
摘要翻译： 一种用于在多处理器数据处理环境中进行直接处理器间通信的系统。 该系统利用传统的直接数据传输手段和大多数微处理器上现有的I / O口指令功能。 要求来自源处理器内部寄存器之一的数据的目标处理器产生一个唯一的地址，该地址指定包含所需数据的寄存器。 地址被发送到数据传输装置，导致数据从指定的源处理器内部寄存器直接传送到目标处理器。 描述完成该直接数据传输功能的具体电路。
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80.发明授权Security-enhanced radio frequency object locator system, method and program storage device 有权安全增强射频对象定位系统，方法和程序存储设备公开(公告)号：US08823491B2
公开(公告)日：2014-09-02
申请号：US13348866
申请日：2012-01-12
CPC分类号： G08B21/24
摘要： Disclosed are an object locator system, a method and a program storage device. In the embodiments, radio frequency identification (RFID) tags are on objects within a defined area and each RFID tag can be activated by an RF activation signal. When a request (e.g., a verbal or keyed-in request) to locate a specific object is received from a specific user, the required permission to locate the object is verified and, optionally, the identity of the specific user is authenticated. Once the required permission is verified and the identity of the specific user is authenticated, one of three RFID readers transmits an RF activation signal. RF response signals received back at the three RFID readers from the specific object's RFID tag are used to triangulate the position of the specific object. Once determined, the position is communicated (e.g., by map display, verbal message, or text message) to the specific user.
摘要翻译： 公开了一种对象定位器系统，方法和程序存储装置。 在实施例中，射频识别（RFID）标签位于限定区域内的对象上，并且每个RFID标签可由RF激活信号激活。 当从特定用户接收到用于定位特定对象的请求（例如，语言或密钥请求）时，验证定位对象的所需许可证，并且可选地，特定用户的身份被认证。 一旦验证了所需许可并且认证了特定用户的身份，三个RFID读取器中的一个发送RF激活信号。 使用从特定对象的RFID标签在三个RFID读取器处接收的RF响应信号来对特定对象的位置进行三角测量。 一旦确定，将位置（例如，通过地图显示，口头消息或文本消息）传达给特定用户。
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