公开(公告)号：US20060267086A1

公开(公告)日：2006-11-30

申请号：US11140780

申请日：2005-05-31

申请人： Toshijaru Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Chung Lam ,  Gerhard Meijer

发明人： Toshijaru Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Chung Lam ,  Gerhard Meijer

IPC分类号： H01L29/76

CPC分类号： H01L27/101 ,  H01L27/115 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  Y10S438/90

摘要： Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers. A temporary conductor may be applied to a series of cells and used to bulk condition the bi-stable layers of the cells. Also, due to the “U” shape of the cells, a cross point wire array may be used to connect a series of cells. The cross point wire array allows the memory elements of each cell to be individually identified and addressed for storing information and also allows for the information stored in the memory elements in all of the cells in the series to be simultaneously erased using a block erase process.

公开(公告)号：US20060289794A1

公开(公告)日：2006-12-28

申请号：US11160156

申请日：2005-06-10

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Peter Mitchell

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Peter Mitchell

IPC分类号： G21G5/00

CPC分类号： G03F7/70341

摘要： An immersion lithography apparatus and method, and a lithographic optical column structure are disclosed for conducting immersion lithography with at least the projection optics of the optical system and the wafer in different fluids at the same pressure. In particular, an immersion lithography apparatus is provided in which a supercritical fluid is introduced about the wafer, and another fluid, e.g., an inert gas, is introduced to at least the projection optics of the optical system at the same pressure to alleviate the need for a special lens. In addition, the invention includes an immersion lithography apparatus including a chamber filled with a supercritical immersion fluid and enclosing a wafer to be exposed and at least a projection optic component of the optical system.

摘要翻译： 公开了一种浸没式光刻设备和方法以及平版印刷光学柱结构，用于在相同压力下用不同流体中的光学系统和晶片的至少投影光学器件进行浸没光刻。 特别地，提供了一种浸没式光刻设备，其中超临界流体被引入晶片周围，并且另一种流体（例如惰性气体）在相同的压力下被引入光学系统的至少投影光学器件以减轻需要 用于特殊镜头。 此外，本发明包括浸没式光刻设备，其包括填充有超临界浸没流体的腔室并且封装要暴露的晶片和至少光学系统的投影光学部件。

公开(公告)号：US20050104139A1

公开(公告)日：2005-05-19

申请号：US11005659

申请日：2004-12-07

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Edward Nowak

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Edward Nowak

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/41 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/2807 ,  H01L21/28114 ,  H01L21/28123 ,  H01L29/1045 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/4991 ,  H01L29/7833

摘要： An FET has a T-shaped gate. The FET has a halo diffusion self-aligned to the bottom portion of the T and an extension diffusion self aligned to the top portion. The halo is thereby separated from the extension implant, and this provides significant advantages. The top and bottom portions of the T-shaped gate can be formed of layers of two different materials, such as germanium and silicon. The two layers are patterned together. Then exposed edges of the bottom layer are selectively chemically reacted and the reaction products are etched away to provide the notch. In another embodiment, the gate is formed of a single gate conductor. A metal is conformally deposited along sidewalls, recess etched to expose a top portion of the sidewalls, and heated to form silicide along bottom portions. The silicide is etched to provide the notch.

摘要翻译： FET具有T形门。 FET具有与T的底部自对准的晕圈扩散，并且与顶部自对准的延伸扩散。 因此，光环与延伸植入物分离，这提供了显着的优点。 T形门的顶部和底部可以由两种不同材料的层形成，例如锗和硅。 两层被图案化在一起。 然后，底层的暴露边缘被选择性地化学反应，并且蚀刻掉反应产物以提供凹口。 在另一个实施例中，栅极由单个栅极导体形成。 金属沿着侧壁共形沉积，凹陷蚀刻以暴露侧壁的顶部，并且被加热以沿底部形成硅化物。 蚀刻硅化物以提供凹口。

公开(公告)号：US20050266627A1

公开(公告)日：2005-12-01

申请号：US11180415

申请日：2005-07-13

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Peter Mitchell ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Peter Mitchell ,  Larry Nesbit

IPC分类号： H01L21/78 ,  H01L27/28 ,  H01L51/30 ,  H01L21/336

CPC分类号： H01L27/283 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/057 ,  Y10S977/70 ,  Y10S977/707 ,  Y10S977/721 ,  Y10S977/724

摘要： Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.

公开(公告)号：US20050130387A1

公开(公告)日：2005-06-16

申请号：US10732953

申请日：2003-12-11

申请人： Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

发明人： Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

IPC分类号： H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L27/01 ,  H01L21/76 ,  H01L31/0392

CPC分类号： H01L27/1203 ,  H01L21/76283 ,  H01L21/84

摘要： To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.

摘要翻译： 为了隔离形成在绝缘体上硅（SOI）衬底上的两个有源区，浅沟槽隔离区填充有液相沉积二氧化硅（LPD-SiO 2），同时避免覆盖有源区 与氧化物。 通过以这种方式选择性地沉积氧化物，与覆盖整个晶片表面的化学气相沉积氧化物层相比，平坦化晶片所需的抛光显着降低。 此外，LPD-SiO 2不包括CVD二氧化硅的生长接缝。 因此，LPD-SiO 2的蚀刻速率在其整个宽度上是均匀的，从而防止存在于现有技术的浅沟槽隔离区域中的空穴和其它蚀刻不规则性，其中生长接缝的蚀刻速率超过 其他氧化物区域。

公开(公告)号：US20070228510A1

公开(公告)日：2007-10-04

申请号：US11760477

申请日：2007-06-08

申请人： Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

发明人： Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

IPC分类号： H01L29/00

CPC分类号： H01L27/1203 ,  H01L21/76283 ,  H01L21/84

摘要： To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.

摘要翻译： 为了隔离形成在绝缘体上硅（SOI）衬底上的两个有源区，浅沟槽隔离区填充有液相沉积二氧化硅（LPD-SiO 2），同时避免覆盖有源区 与氧化物。 通过以这种方式选择性地沉积氧化物，与覆盖整个晶片表面的化学气相沉积氧化物层相比，平坦化晶片所需的抛光显着降低。 此外，LPD-SiO 2不包括CVD二氧化硅的生长接缝。 因此，LPD-SiO 2的蚀刻速率在其整个宽度上是均匀的，从而防止存在于现有技术的浅沟槽隔离区域中的空穴和其它蚀刻不规则性，其中生长接缝的蚀刻速率超过 其他氧化物区域。

公开(公告)号：US20080040696A1

公开(公告)日：2008-02-14

申请号：US11875069

申请日：2007-10-19

申请人： Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

发明人： Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5045 ,  H01L21/76224

摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes shallow trench isolation filled with liquid phase deposited silicon dioxide (LPD-SiO2). The shallow trench isolation region is used to isolate two active regions formed on a silicon-on-insulator (SOI) substrate. By selectively depositing the oxide so that the active areas are not covered with the oxide, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.

摘要翻译： 设计结构体现在用于设计，制造或测试其中设计结构包括填充有液相沉积二氧化硅（LPD-SiO 2）的浅沟槽隔离物的设计的机器可读介质中。 浅沟槽隔离区用于隔离在绝缘体上硅（SOI）衬底上形成的两个有源区。 通过选择性地沉积氧化物使得有源区域不被氧化物覆盖，与覆盖整个晶片表面的化学气相沉积氧化物层相比，平坦化晶片所需的抛光显着降低。 此外，LPD-SiO 2不包括CVD二氧化硅的生长接缝。 因此，LPD-SiO 2的蚀刻速率在其整个宽度上是均匀的，从而防止存在于现有技术的浅沟槽隔离区域中的空穴和其它蚀刻不规则性，其中生长接缝的蚀刻速率超过 其他氧化物区域。

公开(公告)号：US20070235811A1

公开(公告)日：2007-10-11

申请号：US11400596

申请日：2006-04-07

申请人： Toshijaru Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Chung Lam ,  Gerhard Meijer

发明人： Toshijaru Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Chung Lam ,  Gerhard Meijer

IPC分类号： H01L21/336

CPC分类号： H01L27/0629 ,  H01L27/101 ,  H01L27/24

摘要： Disclosed are a semiconductor structure and a method that allow for simultaneous voltage/current conditioning of multiple memory elements in a nonvolatile memory device with multiple memory cells. The structure and method incorporate the use of a resistor connected in series with the memory elements to limit current passing through the memory elements. Specifically, the method and structure incorporate a blanket temporary series resistor on the wafer surface above the memory cells and/or permanent series resistors within the memory cells. During the conditioning process, these resistors protect the transition metal oxide in the individual memory elements from damage (i.e., burn-out), once it has been conditioned.

摘要翻译： 公开了一种半导体结构和方法，其允许在具有多个存储器单元的非易失性存储器件中同时对多个存储器元件进行电压/电流调节。 该结构和方法结合使用与存储器元件串联连接的电阻器来限制电流通过存储器元件。 具体地，该方法和结构在存储器单元上方的晶片表面上和/或存储器单元内的永久串联电阻器上并入一个橡皮布暂时串联电阻器。 在调节过程中，一旦调节了这些电阻，这些电阻就可以保护各个存储元件中的过渡金属氧化物免受损坏（即烧坏）。

公开(公告)号：US20070212810A1

公开(公告)日：2007-09-13

申请号：US11748579

申请日：2007-05-15

申请人： Toshijaru Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Chung Lam ,  Gerhard Meijer

发明人： Toshijaru Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Chung Lam ,  Gerhard Meijer

IPC分类号： H01L21/00

CPC分类号： H01L27/101 ,  H01L27/115 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  Y10S438/90

摘要： Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers. A temporary conductor may be applied to a series of cells and used to bulk condition the bi-stable layers of the cells. Also, due to the “U” shape of the cells, a cross point wire array may be used to connect a series of cells. The cross point wire array allows the memory elements of each cell to be individually identified and addressed for storing information and also allows for the information stored in the memory elements in all of the cells in the series to be simultaneously erased using a block erase process.

摘要翻译： 公开了包含一系列单个或双重存储器单元的非易失性存储器件。 单个存储器单元基本上是“U”形的。 双重存储单元包括两个基本上“U”形的存储单元。 每个存储单元包括具有夹在两个导电层之间的双稳态层的存储元件。 临时导体可以应用于一系列的电池并且用于批量地调节电池的双稳态层。 此外，由于电池的“U”形状，可以使用交叉点线阵列来连接一系列电池。 交叉点线阵列允许每个单元的存储元件被单独识别和寻址用于存储信息，并且还允许使用块擦除处理同时擦除存储在串联中的所有单元中的存储器元件中的信息。

公开(公告)号：US20050237501A1

公开(公告)日：2005-10-27

申请号：US10829623

申请日：2004-04-22

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horal ,  Charles Koburger ,  Peter Mitchell

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horal ,  Charles Koburger ,  Peter Mitchell

IPC分类号： G03B27/52 ,  G03F7/20

CPC分类号： G03F7/70341

摘要： An apparatus, system and method for use with a photolithographic system. In accordance with one embodiment, the photolithographic system of the present invention includes a workpiece support member for supporting a semiconductor wafer. A substantially transparent cover member is disposed over the workpiece support member to form a substantially enclosed workpiece cell therebetween. The enclosed workpiece cell is filled with a first immersion fluid having suitable refractive properties. The cover member, having suitable refractive properties, includes an upper surface contoured to form an open reservoir containing a second immersion fluid, having suitable refractive properties, and in which a final lens element may be immersed during a lithography process.

摘要翻译： 一种用于光刻系统的设备，系统和方法。 根据一个实施例，本发明的光刻系统包括用于支撑半导体晶片的工件支撑构件。 基本上透明的盖构件设置在工件支撑构件上方，以在它们之间形成基本封闭的工件单元。 封闭的工件单元填充有具有合适折射特性的第一浸没流体。 具有合适的折射性质的盖构件包括上表面，其形状为形成具有合适的折射性质的第二浸没流体的开口储存器，并且其中最终的透镜元件可以在光刻工艺期间被浸没。