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    MANUFACTURING METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE
    75.
    发明申请
    MANUFACTURING METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE 有权
    制造半导体结构的制造方法

    公开(公告)号：US20170069528A1

    公开(公告)日：2017-03-09

    申请号：US14845294

    申请日：2015-09-04

    申请人： United Microelectronics Corp.

    发明人： Wei-Hao Huang ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen ,  Shang-Yuan Tsai

    IPC分类号： H01L21/768 ,  H01L21/311

    CPC分类号： H01L21/76802 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/41791 ,  H01L2029/7858

    摘要： The present invention provides a method for forming an opening, including: first, a hard mask material layer is formed on a target layer, next, a tri-layer hard mask is formed on the hard mask material layer, where the tri-layer hard mask includes an bottom organic layer (ODL), a middle silicon-containing hard mask bottom anti-reflection coating (SHB) layer and a top photoresist layer, and an etching process is then performed, to remove parts of the tri-layer hard mask, parts of the hard mask material layer and parts of the target layer in sequence, so as to form at least one opening in the target layer, where during the step for removing parts of the hard mask material layer, a lateral etching rate of the hard mask material layer is smaller than a lateral etching rate of the ODL.

    摘要翻译： 本发明提供一种形成开口的方法，包括：首先在目标层上形成硬掩模材料层，接着在硬掩模材料层上形成三层硬掩模，其中三层硬 掩模包括底部有机层（ODL），中间含硅硬掩模底部防反射涂层（SHB）层和顶部光致抗蚀剂层，然后进行蚀刻工艺以除去三层硬掩模的部分 ，硬掩模材料层的一部分和目标层的一部分，以便在目标层中形成至少一个开口，其中在用于去除硬掩模材料层的部分的步骤期间，侧面蚀刻速率为 硬掩模材料层小于ODL的横向蚀刻速率。

    Semiconductor structure and manufacturing method thereof
    77.
    发明授权
    Semiconductor structure and manufacturing method thereof 有权
    半导体结构及其制造方法

    公开(公告)号：US09543211B1

    公开(公告)日：2017-01-10

    申请号：US14864881

    申请日：2015-09-25

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Yu-Cheng Tung ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  En-Chiuan Liou ,  Wei-Hao Huang ,  Chih-Sen Huang ,  Ching-Wen Hung

    IPC分类号： H01L21/70 ,  H01L21/8234 ,  H01L21/283 ,  H01L27/088

    CPC分类号： H01L21/823437 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L27/088

    摘要： A manufacturing method of a semiconductor structure includes the following steps. Gate structures are formed on a semiconductor substrate. A source/drain contact is formed between two adjacent gate structures. The source/drain contact is recessed by a recessing process. A top surface of the source/drain contact is lower than a top surface of the gate structure after the recessing process. A stop layer is formed on the gate structures and the source/drain contact after the recessing process. A top surface of the stop layer on the source/drain contact is lower than the top surface of the gate structure. A semiconductor structure includes the semiconductor substrate, the gate structures, a gate contact structure, and the source/drain contact. The source/drain contact is disposed between two adjacent gate structures, and the top surface of the source/drain contact is lower than the top surface of the gate structure.

    摘要翻译： 半导体结构的制造方法包括以下步骤。 栅极结构形成在半导体衬底上。 在两个相邻栅极结构之间形成源极/漏极接触。 源极/漏极接触器通过凹陷工艺凹陷。 源极/漏极接触件的顶表面在凹陷过程之后低于栅极结构的顶表面。 在凹陷过程之后，在栅极结构和源极/漏极触点上形成阻挡层。 源极/漏极接触点上的阻挡层的顶表面低于栅极结构的顶表面。 半导体结构包括半导体衬底，栅极结构，栅极接触结构和源极/漏极接触。 源极/漏极触点设置在两个相邻的栅极结构之间，源极/漏极接触的顶表面低于栅极结构的顶部表面。

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING METAL GATE
    78.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING METAL GATE 有权
    制造具有金属栅的半导体器件的方法

    公开(公告)号：US20160380077A1

    公开(公告)日：2016-12-29

    申请号：US15263349

    申请日：2016-09-12

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

    IPC分类号： H01L29/66 ,  H01L29/51 ,  H01L27/092 ,  H01L29/40 ,  H01L29/423 ,  H01L21/8238

    CPC分类号： H01L29/66545 ,  H01L21/823842 ,  H01L27/0883 ,  H01L27/092 ,  H01L29/165 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/66628

    摘要： A method for manufacturing a semiconductor device having metal gates includes following steps. A substrate including a first transistor and a second transistor formed thereon is provided. The first transistor includes a first gate trench and the second transistor includes a second gate trench. A patterned first work function metal layer is formed in the first gate trench and followed by forming a second sacrificial masking layer respectively in the first gate trench and the second gate trench. An etching process is then performed to form a U-shaped first work function metal layer in the first gate trench. Subsequently, a two-step etching process including a strip step and a wet etching step is performed to remove the second sacrificial masking layer and portions of the U-shaped first work function metal layer to form a taper top on the U-shaped first work function metal layer in the first gate trench.

    摘要翻译： 制造具有金属栅极的半导体器件的方法包括以下步骤。 提供了包括形成在其上的第一晶体管和第二晶体管的衬底。 第一晶体管包括第一栅极沟槽，第二晶体管包括第二栅极沟槽。 在第一栅极沟槽中形成图案化的第一功函数金属层，然后分别在第一栅极沟槽和第二栅极沟槽中形成第二牺牲掩模层。 然后进行蚀刻工艺以在第一栅极沟槽中形成U形的第一功函数金属层。 随后，执行包括条带步骤和湿蚀刻步骤的两步蚀刻工艺，以去除第二牺牲掩模层和U形第一功函数金属层的部分以在U形第一工件上形成锥形顶部 功能金属层在第一栅极沟槽中。

    SEMICONDUCTOR DEVICE
    79.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20160322468A1

    公开(公告)日：2016-11-03

    申请号：US14723467

    申请日：2015-05-28

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen ,  Wei-Hao Huang

    IPC分类号： H01L29/423 ,  H01L29/51 ,  H01L23/535

    CPC分类号： H01L29/42364 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/51 ,  H01L29/518 ,  H01L29/785

    摘要： A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure on the substrate; an interlayer dielectric (ILD) around the gate structure; a first contact plug in the ILD layer; a second dielectric layer on the ILD layer; a second contact plug in the second dielectric layer and electrically connected to the first contact plug; and a spacer between the second contact plug and the second dielectric layer.

    摘要翻译： 公开了一种半导体器件。 半导体器件包括：衬底; 基板上的栅极结构; 围绕栅极结构的层间电介质（ILD）; ILD层中的第一接触插塞; ILD层上的第二介电层; 第二接触插塞在第二电介质层中并电连接到第一接触插塞; 以及在第二接触插塞和第二电介质层之间的间隔物。

    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    80.
    发明申请
    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20160163532A1

    公开(公告)日：2016-06-09

    申请号：US14562768

    申请日：2014-12-07

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  En-Chiuan Liou ,  Chieh-Te Chen

    IPC分类号： H01L21/02 ,  H01L21/033 ,  H01L21/027 ,  H01L21/311

    CPC分类号： H01L21/0206 ,  H01L21/02186 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897

    摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a hard mask on the gate structure and the ILD layer; forming a first patterned mask layer on the hard mask; using the first patterned mask layer to remove part of the hard mask for forming a patterned hard mask; and utilizing a gas to strip the first patterned mask layer while forming a protective layer on the patterned hard mask, wherein the gas is selected from the group consisting of N2 and O2.

    摘要翻译： 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上至少具有栅极结构的衬底和围绕栅极结构的层间电介质（ILD）层; 在栅极结构和ILD层上形成硬掩模; 在硬掩模上形成第一图案化掩模层; 使用第一图案化掩模层去除用于形成图案化硬掩模的硬掩模的一部分; 并且利用气体剥离第一图案化掩模层，同时在图案化的硬掩模上形成保护层，其中气体选自N2和O2。