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71.发明申请Modulation-doped halos in quantum well field-effect transistors, apparatus made therewith, and methods of using same 有权量子阱场效应晶体管中的调制掺杂光晕，其制造的装置及其使用方法公开(公告)号：US20100213441A1
公开(公告)日：2010-08-26
申请号：US12378828
申请日：2009-02-20
申请人： Ravi Pillarisetty , Titash Rakshit , Mantu Hudait , Marko Radosavljevic , Gilbert Dewey , Benjamin Chu-Kung
发明人： Ravi Pillarisetty , Titash Rakshit , Mantu Hudait , Marko Radosavljevic , Gilbert Dewey , Benjamin Chu-Kung
IPC分类号： H01L29/80 , H01L21/3205
CPC分类号： H01L29/122 , B82Y10/00 , H01L29/045 , H01L29/205 , H01L29/207 , H01L29/4236 , H01L29/51 , H01L29/66462 , H01L29/7785
摘要： A quantum well (QW) layer is provided in a semiconductive device. The QW layer is provided with a beryllium-doped halo layer in a barrier structure below the QW layer. The semiconductive device includes InGaAs bottom and top barrier layers respectively below and above the QW layer. The semiconductive device also includes a high-k gate dielectric layer that sits on the InP spacer first layer in a gate recess. A process of forming the QW layer includes using an off-cut semiconductive substrate.
摘要翻译： 在半导体器件中提供量子阱（QW）层。 QW层在QW层下面的阻挡结构中设置有铍掺杂卤素层。 半导体器件包括分别在QW层下方和上方的InGaAs底部和顶部势垒层。 半导体器件还包括位于栅极凹槽中的InP间隔物第一层上的高k栅介质层。 形成QW层的方法包括使用切断的半导体衬底。
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72.发明申请NON-PLANAR SEMICONDUCTOR DEVICE HAVING GROUP III-V MATERIAL ACTIVE REGION WITH MULTI-DIELECTRIC GATE STACK 审中-公开具有多层电极堆叠的III-V族材料活性区域的非平面半导体器件公开(公告)号：US20160240612A1
公开(公告)日：2016-08-18
申请号：US15135262
申请日：2016-04-21
IPC分类号： H01L29/06 , H01L29/66 , H01L29/423 , H01L29/51 , H01L29/201 , H01L29/205
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y99/00 , H01L29/0665 , H01L29/201 , H01L29/205 , H01L29/408 , H01L29/4236 , H01L29/42364 , H01L29/42392 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/78696
摘要： Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
摘要翻译： 描述具有多电介质栅叠层的具有III-V族材料的区域的非平面半导体器件。 例如，半导体器件包括设置在衬底上的异质结构。 异质结构包括具有沟道区的三维III-V族材料体。 源极和漏极材料区域设置在三维III-V族材料体上方。 在源极和漏极材料区域中布置沟槽，其将源极区域与漏极区域分离，并且暴露沟道区域的至少一部分。 栅极堆叠设置在沟槽中和沟道区域的暴露部分上。 栅极堆叠包括第一和第二电介质层和栅电极。
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73.发明授权Non-planar semiconductor device having channel region with low band-gap cladding layer 有权具有低带隙包层的沟道区域的非平面半导体器件公开(公告)号：US08785909B2
公开(公告)日：2014-07-22
申请号：US13629148
申请日：2012-09-27
申请人： Marko Radosavljevic , Gilbert Dewey , Benjamin Chu-Kung , Dipanjan Basu , Sanaz K. Gardner , Satyarth Suri , Ravi Pillarisetty , Niloy Mukherjee , Han Wui Then , Robert S. Chau
发明人： Marko Radosavljevic , Gilbert Dewey , Benjamin Chu-Kung , Dipanjan Basu , Sanaz K. Gardner , Satyarth Suri , Ravi Pillarisetty , Niloy Mukherjee , Han Wui Then , Robert S. Chau
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/068 , H01L29/201 , H01L29/401 , H01L29/42392 , H01L29/66469 , H01L29/775 , H01L29/785 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： Non-planar semiconductor devices having channel regions with low band-gap cladding layers are described. For example, a semiconductor device includes a vertical arrangement of a plurality of nanowires disposed above a substrate. Each nanowire includes an inner region having a first band gap and an outer cladding layer surrounding the inner region. The cladding layer has a second, lower band gap. A gate stack is disposed on and completely surrounds the channel region of each of the nanowires. The gate stack includes a gate dielectric layer disposed on and surrounding the cladding layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the channel regions of the nanowires.
摘要翻译： 描述具有低带隙包层的沟道区的非平面半导体器件。 例如，半导体器件包括布置在衬底上方的多个纳米线的垂直布置。 每个纳米线包括具有第一带隙的内部区域和围绕内部区域的外部包层。 包层具有第二较低带隙。 栅堆叠设置在每个纳米线的沟道区上并完全包围。 栅极堆叠包括设置在包层上并围绕着包层的栅极电介质层和设置在栅极介电层上的栅电极。 源区和漏区设置在纳米线的沟道区的两侧。
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74.发明申请NON-PLANAR SEMICONDUCTOR DEVICE HAVING GROUP III-V MATERIAL ACTIVE REGION WITH MULTI-DIELECTRIC GATE STACK 有权具有多层电极堆叠的III-V族材料活性区域的非平面半导体器件公开(公告)号：US20140084343A1
公开(公告)日：2014-03-27
申请号：US13629154
申请日：2012-09-27
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y99/00 , H01L29/0665 , H01L29/201 , H01L29/205 , H01L29/408 , H01L29/4236 , H01L29/42364 , H01L29/42392 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/78696
摘要： Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
摘要翻译： 描述具有多电介质栅叠层的具有III-V族材料的区域的非平面半导体器件。 例如，半导体器件包括设置在衬底上的异质结构。 异质结构包括具有沟道区的三维III-V族材料体。 源极和漏极材料区域设置在三维III-V族材料体上方。 在源极和漏极材料区域中布置沟槽，其将源极区域与漏极区域分离，并且暴露沟道区域的至少一部分。 栅极堆叠设置在沟槽中和沟道区域的暴露部分上。 栅极堆叠包括第一和第二电介质层和栅电极。
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公开(公告)号：US20130307513A1
公开(公告)日：2013-11-21
申请号：US13976414
申请日：2011-12-19
申请人： Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
发明人： Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
IPC分类号： H01L29/775 , G05F3/02 , H01L29/66
CPC分类号： H01L29/0673 , B82Y10/00 , G05F3/02 , H01L21/02603 , H01L21/02636 , H01L21/225 , H01L21/283 , H01L21/30604 , H01L21/31 , H01L21/31116 , H01L21/32133 , H01L21/324 , H01L29/04 , H01L29/0676 , H01L29/068 , H01L29/2003 , H01L29/41725 , H01L29/42356 , H01L29/42392 , H01L29/66439 , H01L29/66462 , H01L29/66469 , H01L29/775 , H01L29/78696
摘要： Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.
摘要翻译： 晶体管适用于高电压和高频工作。 纳米线垂直或水平地布置在基底上。 纳米线的纵向长度被限定为第一半导体材料的沟道区域，与沟道区域的第一端电耦合的源极区域，与沟道区域的第二端电耦合的漏极区域和外部漏极 区域设置在沟道区域和漏极区域之间。 外在漏极区具有比第一半导体更宽的带隙。 包括栅极导体和栅极绝缘体的栅极堆叠器完全同轴地包裹在沟道区域周围，漏极和源极触点类似地同轴地围绕漏极和源极区域包裹。
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公开(公告)号：US08211771B2
公开(公告)日：2012-07-03
申请号：US13216569
申请日：2011-08-24
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L29/0657 , H01L29/0834 , H01L29/42312 , H01L29/66356 , H01L29/7391
摘要： A microelectronic device includes a P-I-N (p+ region, intrinsic semiconductor, and n+ region) semiconductive body with a first gate and a second gate. The first gate is a gate stack disposed on an upper surface plane, and the second gate accesses the semiconductive body from a second plane that is out of the first plane.
摘要翻译： 微电子器件包括具有第一栅极和第二栅极的P-I-N（p +区域，本征半导体和n +区域）半导体。 第一栅极是设置在上表面平面上的栅极堆叠，并且第二栅极从超出第一平面的第二平面访问半导体本体。
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公开(公告)号：US08093584B2
公开(公告)日：2012-01-10
申请号：US12317468
申请日：2008-12-23
CPC分类号： H01L29/4236 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/66462 , H01L29/7783
摘要： A self-aligned replacement metal gate QWFET device comprises a III-V quantum well layer formed on a substrate, a III-V barrier layer formed on the quantum well layer, a III-V etch stop layer formed on the III-V barrier layer, a III-V source extension region formed on the III-V etch stop layer and having a first sidewall, a source region formed on the III-V source extension region and having a second sidewall, a III-V drain extension region formed on the III-V etch stop layer and having a third sidewall, a drain region formed on the III-V drain extension region and having a fourth sidewall, a conformal high-k gate dielectric layer formed on the first, second, third, and fourth sidewalls and on a top surface of the etch stop layer, and a metal layer formed on the high-k gate dielectric layer.
摘要翻译： 自对准替代金属栅极QWFET器件包括形成在衬底上的III-V量子阱层，形成在量子阱层上的III-V势垒层，形成在III-V势垒层上的III-V蚀刻停止层 ，III-V源延伸区，形成在III-V蚀刻停止层上，并具有第一侧壁，形成在III-V源极延伸区上并具有第二侧壁的源极区， III-V蚀刻停止层并具有第三侧壁，形成在III-V漏极延伸区上并具有第四侧壁的漏极区，形成在第一，第二，第三和第四上的共形高k栅介质层 侧壁和蚀刻停止层的顶表面，以及形成在高k栅极电介质层上的金属层。
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公开(公告)号：US08063447B2
公开(公告)日：2011-11-22
申请号：US12221802
申请日：2008-08-06
IPC分类号： H01L29/78
CPC分类号： H01L21/26586 , H01L29/0657 , H01L29/0834 , H01L29/42312 , H01L29/66356 , H01L29/7391
摘要： A microelectronic device includes a P-I-N (p+ region, intrinsic semiconductor, and n+ region) semiconductive body with a first gate and a second gate. The first gate is a gate stack disposed on an upper surface plane, and the second gate accesses the semiconductive body from a second plane that is out of the first plane.
摘要翻译： 微电子器件包括具有第一栅极和第二栅极的P-I-N（p +区域，本征半导体和n +区域）半导体。 第一栅极是设置在上表面平面上的栅极堆叠，并且第二栅极从超出第一平面的第二平面访问半导体本体。
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公开(公告)号：US20100155701A1
公开(公告)日：2010-06-24
申请号：US12317468
申请日：2008-12-23
IPC分类号： H01L29/66
CPC分类号： H01L29/4236 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/66462 , H01L29/7783
摘要： A self-aligned replacement metal gate QWFET device comprises a III-V quantum well layer formed on a substrate, a III-V barrier layer formed on the quantum well layer, a III-V etch stop layer formed on the III-V barrier layer, a III-V source extension region formed on the III-V etch stop layer and having a first sidewall, a source region formed on the III-V source extension region and having a second sidewall, a III-V drain extension region formed on the III-V etch stop layer and having a third sidewall, a drain region formed on the III-V drain extension region and having a fourth sidewall, a conformal high-k gate dielectric layer formed on the first, second, third, and fourth sidewalls and on a top surface of the etch stop layer, and a metal layer formed on the high-k gate dielectric layer.
摘要翻译： 自对准替代金属栅极QWFET器件包括形成在衬底上的III-V量子阱层，形成在量子阱层上的III-V势垒层，形成在III-V势垒层上的III-V蚀刻停止层 ，III-V源延伸区，形成在III-V蚀刻停止层上，并具有第一侧壁，形成在III-V源极延伸区上并具有第二侧壁的源极区， III-V蚀刻停止层并具有第三侧壁，形成在III-V漏极延伸区上并具有第四侧壁的漏极区，形成在第一，第二，第三和第四上的共形高k栅介质层 侧壁和蚀刻停止层的顶表面，以及形成在高k栅极电介质层上的金属层。
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公开(公告)号：US20100032763A1
公开(公告)日：2010-02-11
申请号：US12221802
申请日：2008-08-06
IPC分类号： H01L29/78 , H01L21/336 , H01L21/28
CPC分类号： H01L21/26586 , H01L29/0657 , H01L29/0834 , H01L29/42312 , H01L29/66356 , H01L29/7391
摘要： A microelectronic device includes a P-I-N (p+ region, intrinsic semiconductor, and n+ region) semiconductive body with a first gate and a second gate. The first gate is a gate stack disposed on an upper surface plane, and the second gate accesses the semiconductive body from a second plane that is out of the first plane.
摘要翻译： 微电子器件包括具有第一栅极和第二栅极的P-I-N（p +区域，本征半导体和n +区域）半导体。 第一栅极是设置在上表面平面上的栅极堆叠，并且第二栅极从超出第一平面的第二平面访问半导体本体。
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