公开(公告)号：US20170141200A1

公开(公告)日：2017-05-18

申请号：US14944224

申请日：2015-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan-Hsiang Chang ,  Shen-De Wang ,  Chih-Chien Chang ,  JIANJUN YANG ,  Aaron Chen

IPC: H01L29/423 ,  H01L21/28 ,  H01L21/265 ,  H01L21/321 ,  H01L27/115 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/788 ,  H01L29/51 ,  H01L29/66 ,  H01L21/223

CPC classification number: H01L29/42328 ,  H01L21/26586 ,  H01L21/28273 ,  H01L21/28562 ,  H01L21/31111 ,  H01L21/321 ,  H01L21/32133 ,  H01L27/11521 ,  H01L28/00 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/788

Abstract: A flash cell includes a gate and an erase gate. The gate is disposed on a substrate, wherein the gate includes a control gate on the substrate and a floating gate having a tip between the substrate and the control gate. The erase gate is disposed beside the gate, wherein the tip points toward the erase gate. The present invention also provides a flash cell forming process including the following steps. A gate is formed on a substrate, wherein the gate includes a floating gate on the substrate. An implantation process is performed on a side part of the floating gate, thereby forming a first doped region in the side part. At least a part of the first doped region is oxidized, thereby forming a floating gate having a tip.

公开(公告)号：US20170117372A1

公开(公告)日：2017-04-27

申请号：US14923409

申请日：2015-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： DONGDONG LI ,  Ko-Chi Chen ,  Shen-De Wang

IPC: H01L29/423 ,  H01L29/788 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L29/42328 ,  H01L27/11534 ,  H01L29/42336 ,  H01L29/66825

Abstract: The present invention provides a semiconductor device, including a substrate with a memory region and a logic region, the substrate having a recess disposed in the memory region, a logic gate stack disposed in the logic region, and a non-volatile memory disposed in the recess. The non-volatile memory includes at least two floating gates and at least two control gates disposed on the floating gates, where each floating gate has a step-shaped bottom, and the step-shaped bottom includes a first bottom surface and a second bottom surface lower than the first bottom surface.

公开(公告)号：US20170110469A1

公开(公告)日：2017-04-20

申请号：US14950424

申请日：2015-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Ko-Chi Chen ,  Shen-De Wang

IPC: H01L27/115 ,  H01L29/423

CPC classification number: H01L27/11578 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/4236

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, a non-volatile memory cell, and a gate stack. The non-volatile memory cell is formed in the semiconductor substrate, and a top surface of the non-volatile memory cell is coplanar with or below a top surface of the semiconductor substrate. The gate stack is formed on the semiconductor substrate.

公开(公告)号：US09331185B2

公开(公告)日：2016-05-03

申请号：US14505513

申请日：2014-10-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Huei Huang ,  Shen-De Wang ,  Wen-Chung Chang ,  Feng-Ji Tsai ,  Chien-Hung Chen

IPC: H01L21/336 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/66833 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/792

Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a gate structure, performing a first oxidation process to form a first SiO layer at least covering a bottom corner of the conductive layer, performing a first etching process to remove the first SiO layer and a portion of the dielectric layer to form a cavity, performing a second oxidation process to form a second SiO layer covering sidewalls of the cavity and a third SiO layer covering a surface of the substrate, forming a first SiN layer filling in the cavity and covering the gate structure on the substrate, and removing a portion of the first SiN layer to form a SiN structure including a foot portion filling in the cavity and an erection portion upwardly extended from the foot portion, and the erection portion covering sidewalls of the gate structure.

Abstract translation: 一种用于制造非易失性存储结构的方法包括提供具有栅极结构的衬底，执行第一氧化工艺以形成至少覆盖导电层的底角的第一SiO层，执行第一蚀刻工艺以除去第一 SiO层和所述电介质层的一部分以形成空腔，执行第二氧化工艺以形成覆盖所述空腔的侧壁的第二SiO层和覆盖所述衬底的表面的第三SiO层，形成填充在所述腔中的第一SiN层 并且覆盖衬底上的栅极结构，并且去除第一SiN层的一部分以形成SiN结构，其包括填充在空腔中的脚部和从脚部向上延伸的勃起部，以及覆盖侧壁的安装部 门结构。

公开(公告)号：US20150270277A1

公开(公告)日：2015-09-24

申请号：US14220122

申请日：2014-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Shan Chiu ,  Shen-De Wang ,  ZHEN CHEN ,  Yuan-Hsiang Chang ,  Chih-Chien Chang ,  JIANJUN YANG ,  Wei Ta

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L21/3213 ,  H01L21/02

CPC classification number: H01L29/66833 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/792

Abstract: The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof.

Abstract translation: 本发明提供了一种存储单元，其包括基板，栅极介电层，图案化材料层，选择栅极和控制栅极。 栅介电层设置在基板上。 图案化材料层设置在基底上，其中图案化材料层包括垂直部分和水平部分。 选择栅极设置在栅极电介质层和图案化材料层的垂直部分的一侧。 控制栅极设置在图案化材料层的水平部分上并且在垂直部分的另一侧，其中垂直部分在选择栅极的顶部上方突出。 本发明还提供了存储单元的另一实施例及其制造方法。

公开(公告)号：US20140198574A1

公开(公告)日：2014-07-17

申请号：US13741442

申请日：2013-01-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shen-De Wang ,  Wen-Chung Chang ,  Ya-Huei Huang ,  Feng-Ji Tsai ,  Chien-Hung Chen

IPC: G11C16/14 ,  G11C16/10 ,  H01L27/088

CPC classification number: G11C16/14 ,  G11C16/0475 ,  G11C16/10 ,  H01L21/28282 ,  H01L27/088 ,  H01L27/11565 ,  H01L27/11568

Abstract: A manipulating method of a nonvolatile memory is provided and comprises following steps. The nonvolatile memory having a plurality of memory cell is provided. Two adjacent memory cells correspond to one bit and comprise a substrate, a first and another first doping regions, a second doping region, a charge trapping layer, a control gate, a first bit line, a source line and a second bit line different from the first bit line. A first and a second channel are formed. The charge trapping layer is disposed on the first and the second channels. The two adjacent memory cells are programmed by following steps. A first positive and negative voltages are applied to the control gate between the first and the second doping regions and the control gate between the second and the another first doping regions, respectively. A first voltage is applied to the source line.

Abstract translation: 提供了一种非易失性存储器的操作方法，包括以下步骤。 提供具有多个存储单元的非易失性存储器。 两个相邻的存储器单元对应于一个位，并且包括基板，第一和第二第一掺杂区域，第二掺杂区域，电荷俘获层，控制栅极，第一位线，源极线和与 第一个位线。 形成第一和第二通道。 电荷捕获层设置在第一和第二通道上。 通过以下步骤对相邻的两个存储单元进行编程。 第一正电压和负电压分别施加到第一和第二掺杂区域之间的控制栅极以及第二和第二掺杂区域之间的控制栅极。 第一个电压被施加到源极线。

公开(公告)号：US20140092689A1

公开(公告)日：2014-04-03

申请号：US13633732

申请日：2012-10-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Feng-Ji Tsai ,  Shen-De Wang ,  Wen-Chung Chang ,  Ya-Huei Huang ,  Chien-Hung Chen

IPC: G11C16/10 ,  H01L29/792 ,  G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/26 ,  H01L29/4234 ,  H01L29/42348 ,  H01L29/7923

Abstract: A method for programming a non-volatile memory cell is described. The memory cell includes a substrate, a gate over the substrate, a charge-trapping structure at least between the substrate and the gate, and first and second S/D regions in the substrate beside the gate. The method includes performing a channel-initiated secondary electron (CHISEL) injection process to inject electrons to the charge-trapping structure.

Abstract translation: 描述用于编程非易失性存储器单元的方法。 存储单元包括衬底，衬底上的栅极，至少在衬底和栅极之间的电荷捕获结构以及栅极旁边的衬底中的第一和第二S / D区域。 该方法包括执行通道引发的二次电子（CHISEL）注入过程以将电子注入电荷捕获结构。