公开(公告)号：US20170084739A1

公开(公告)日：2017-03-23

申请号：US14886108

申请日：2015-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Chia-Min Hung

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L21/441 ,  H01L21/4763 ,  H01L21/471 ,  H01L21/4757 ,  H01L29/24 ,  H01L29/66

CPC classification number: H01L29/7823 ,  H01L21/441 ,  H01L21/471 ,  H01L21/47573 ,  H01L21/4763 ,  H01L21/47635 ,  H01L29/0611 ,  H01L29/0653 ,  H01L29/24 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41725 ,  H01L29/66689 ,  H01L29/66969 ,  H01L29/7816

Abstract: The present invention provides a laterally diffused metal-oxide-semiconductor (LDMOS) transistor and a manufacturing method thereof. The LDMOS transistor includes a semiconductor substrate, an insulation structure, agate structure, and a plurality of floating electrodes. The insulation structure is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate. The floating electrodes are embedded in the insulation structure, wherein the floating electrode closest to the gate structure protrudes from a top surface of the insulation structure or the gate structure includes at least one branch portion embedded in the insulation structure, and the floating electrodes are separated from the gate structure.

公开(公告)号：US20170047397A1

公开(公告)日：2017-02-16

申请号：US14859348

申请日：2015-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L29/7836

Abstract: A method for fabricating isolation device is disclosed. The method includes the steps of: providing a substrate; forming a shallow trench isolation (STI) in the substrate, the STI includes a first STI and a second STI, and the first STI surrounds a first device region and the second STI surrounds a second device region; forming a first doped region between and contact the first STI and the second STI; and forming a first gate structure on the first doped region, the first STI and the second STI.

Abstract translation: 公开了一种用于制造隔离装置的方法。 该方法包括以下步骤：提供衬底; 在衬底中形成浅沟槽隔离（STI），STI包括第一STI和第二STI，并且第一STI围绕第一器件区域，第二STI围绕第二器件区域; 在第一STI和第二STI之间形成第一掺杂区域并接触第一STI; 以及在所述第一掺杂区域上形成第一栅极结构，所述第一STI和所述第二STI。

公开(公告)号：US09570451B1

公开(公告)日：2017-02-14

申请号：US15151483

申请日：2016-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Tun-Jen Cheng

IPC: H01L21/338 ,  H01L27/11 ,  H01L21/266 ,  H01L21/027 ,  H01L21/265

CPC classification number: H01L27/1116 ,  H01L21/0273 ,  H01L21/26586 ,  H01L21/823412 ,  H01L27/1104 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66492

Abstract: A method of forming semiconductor devices. First, a substrate is provided, and a first implant area and a second implant area are defined in a mask pattern. Subsequently, a resist layer on the substrate is patterned using the mask pattern to form a first opening exposing the first implant area and a second opening to expose the second implant area. After that, an ion implantation process including a partial shadowing ion implant is processed, wherein the second implant area is implanted by the partial shadowing ion implant to a predetermined concentration, and the first implant area is substantially not implanted by the partial shadowing ion implant.

Abstract translation: 一种形成半导体器件的方法。 首先，提供基板，并且以掩模图案限定第一注入区域和第二注入区域。 随后，使用掩模图案对衬底上的抗蚀剂层进行构图，以形成暴露第一注入区域的第一开口和暴露第二注入区域的第二开口。 之后，处理包括部分阴离子离子注入的离子注入工艺，其中通过部分阴离子注入将第二注入区植入预定浓度，并且第一注入区基本上不被部分阴离子注入植入。

公开(公告)号：US09490316B2

公开(公告)日：2016-11-08

申请号：US14542672

申请日：2014-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Chung Yang ,  Shih-Yin Hsiao

IPC: H01L21/31 ,  H01L21/469 ,  H01L29/06 ,  H01L21/762 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/0653 ,  H01L21/7621 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a silicon oxide layer disposed on the substrate, and at least part of a gate electrode covering the silicon oxide layer. A top surface of the silicon oxide layer is in the shape of plural hills. The silicon oxide layer can provide low on-state resistance for the semiconductor structure.

Abstract translation: 提供半导体结构。 半导体结构包括衬底，设置在衬底上的氧化硅层和覆盖氧化硅层的栅电极的至少一部分。 氧化硅层的上表面为多个山丘的形状。 氧化硅层可以为半导体结构提供低导通电阻。

公开(公告)号：US09406771B1

公开(公告)日：2016-08-02

申请号：US14854161

申请日：2015-09-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Hsueh-Chun Hsiao ,  Tzu-Yun Chang ,  Ching-Chung Yang

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L21/28 ,  H01L21/265

CPC classification number: H01L29/4983 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28105 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4916 ,  H01L29/7833

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate; a first and a second ion implantation regions of a first conductive type; a source and a drain diffusion regions formed in the first and the second ion implantation regions respectively; a channel diffusion region formed between the first and the second ion implantation regions; a gate layer disposed above the channel diffusion region and located between the source and the drain diffusion regions; and a third ion implantation region of a second conductive type formed in the gate layer, which extends in a first direction. The third ion implantation region is located above and covers two side portions of the channel diffusion region, the two side portions are adjacent to two edges, extending in a second direction perpendicular to the first direction, of the channel diffusion region.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括基板; 第一导电类型的第一和第二离子注入区域; 在第一和第二离子注入区域中形成的源极和漏极扩散区域; 形成在第一和第二离子注入区之间的沟道扩散区; 栅极层，其设置在所述沟道扩散区域的上方且位于所述源极和漏极扩散区域之间; 以及形成在所述栅极层中的沿第一方向延伸的第二导电类型的第三离子注入区。 第三离子注入区域位于沟道扩散区域的上方并覆盖两个侧面部分，两个侧面部分与沟道扩散区域的垂直于第一方向的第二方向延伸的两个边缘相邻。

公开(公告)号：US09349818B2

公开(公告)日：2016-05-24

申请号：US14519153

申请日：2014-10-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66545 ,  H01L21/76895 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/401 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/66568 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835

Abstract: A MOS transistor device includes a substrate including a gate formed thereon, and a spacer being formed on a sidewall of the gate; a source region and a drain region formed in the substrate; and at least a first dummy contact formed above the substrate on a drain side of the gate. More important, the first dummy contact is formed apart from a surface of the substrate.

Abstract translation: MOS晶体管器件包括其上形成有栅极的衬底和形成在栅极的侧壁上的间隔物; 形成在所述基板中的源极区域和漏极区域; 以及形成在栅极的漏极侧的衬底上方的至少第一虚拟接触。 更重要的是，第一虚拟接触件与衬底的表面分开形成。

公开(公告)号：US20230326801A1

公开(公告)日：2023-10-12

申请号：US18335154

申请日：2023-06-15

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Kuan-Liang Liu

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/02 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8249 ,  H01L29/423

CPC classification number: H01L21/823425 ,  H01L29/0607 ,  H01L27/0251 ,  H01L29/4925 ,  H01L29/7832 ,  H01L21/8249 ,  H01L29/7835 ,  H01L21/823437 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/78

Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping the gate region.

公开(公告)号：US20210335669A1

公开(公告)日：2021-10-28

申请号：US17367150

申请日：2021-07-02

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Kuan-Liang Liu

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/02 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8249 ,  H01L29/423

Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping the gate region.

公开(公告)号：US10796964B2

公开(公告)日：2020-10-06

申请号：US16428651

申请日：2019-05-31

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Kuan-Liang Liu

IPC: H01L29/06 ,  H01L27/02 ,  H01L21/8249 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423

Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.

公开(公告)号：US20200212201A1

公开(公告)日：2020-07-02

申请号：US16813768

申请日：2020-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu ,  Ching-Chung Yang ,  Ping-Hung Chiang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

Abstract: A high voltage semiconductor device and a manufacturing method thereof are provided in the present invention. A recess is formed in a semiconductor substrate, and a gate dielectric layer and a main gate structure are formed in the recess. Therefore, the high voltage semiconductor device formed by the manufacturing method of the present invention may include the main gate structure lower than a top surface of an isolation structure formed in the semiconductor substrate. Problems about integrated manufacturing processes of the high voltage semiconductor device and other kinds of semiconductor devices when the gate structure is relatively high because of the thicker gate dielectric layer required in the high voltage semiconductor device may be improved accordingly.