公开(公告)号：US06531371B2

公开(公告)日：2003-03-11

申请号：US09894922

申请日：2001-06-28

申请人： Sheng Teng Hsu ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Wei-Wei Zhuang

IPC分类号： H01L2120

CPC分类号： G11C11/15 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C2213/31 ,  G11C2213/77 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： Resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. Memory circuits are provided to aid in the programming and read out of the bit region.

摘要翻译： 提供了电阻式交叉点存储器件以及制造和使用方法。 存储器件包括插在上电极和下电极之间的钙钛矿材料的有源层。 在上电极和下电极的交叉点处位于有源层内的位区域具有响应于施加一个或更多个电压脉冲而可以在值范围内变化的电阻率。 可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。 提供存储器电路以帮助编程和读出位区域。

公开(公告)号：US06472337B1

公开(公告)日：2002-10-29

申请号：US10020471

申请日：2001-10-30

申请人： Wei-Wei Zhuang ,  David R. Evans

发明人： Wei-Wei Zhuang ,  David R. Evans

IPC分类号： H01L2131

CPC分类号： H01L21/31625 ,  C01G25/02 ,  C01G27/02 ,  C07F7/003 ,  C23C16/405 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/3141

摘要： A method of making a precursor for a thin film formed by chemical vapor deposition processes, includes mixing ZCl4 with H(tmhd)3 solvent and benzene to form a solution, where Z is an element taken from the group of elements consisting of hafnium and zirconium; refluxing the solution for twelve hours in an argon atmosphere; removing the solvents via vacuum, thereby producing a solid compound; and sublimating the compound at 200° C. in a near vacuum of 0.1 mmHg. A ZOx precursor, for use in a chemical vapor deposition process, includes a Z-containing compound taken from the group of compounds consisting of ZCl(tmhd)3 and ZCl2(tmhd)2.

摘要翻译： 通过化学气相沉积法制备薄膜前体的方法包括将ZCl4与H（tmhd）3溶剂和苯混合形成溶液，其中Z是从由铪和锆组成的元素组成的元素 ; 在氩气氛中回流12小时; 通过真空除去溶剂，从而产生固体化合物; 并在0.1mmHg的接近真空下在200℃升华该化合物。 用于化学气相沉积方法的ZOx前体包括从ZCl（tmhd）3和ZCl 2（tmhd）2组成的化合物组中取代的含Z化合物。

公开(公告)号：US06441417B1

公开(公告)日：2002-08-27

申请号：US09820022

申请日：2001-03-28

申请人： Fengyan Zhang ,  Yanjun Ma ,  Jer-Shen Maa ,  Wei-Wei Zhuang ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Yanjun Ma ,  Jer-Shen Maa ,  Wei-Wei Zhuang ,  Sheng Teng Hsu

IPC分类号： H01L2972

CPC分类号： H01L21/28291 ,  H01L21/31604 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/516

摘要： A thin film structure includes a substantially single-phase, c-axis PGO film on an insulator for use in metal ferroelectric insulator semiconductor single transistor non-volatile memory applications. The PGO on insulator structure can also be used in capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices. In a preferred embodiment, the PGO film is deposited on a Zirconium Oxide insulator layer.

摘要翻译： 薄膜结构包括用于金属铁电绝缘体半导体单晶体管非易失性存储器应用的绝缘体上的基本单相c轴PGO膜。 PGO绝缘体结构也可用于电容器，热释电红外传感器，光学显示器，光开关，压电换能器和表面声波器件中。 在优选实施例中，PGO膜沉积在氧化锆绝缘体层上。

公开(公告)号：US07323349B2

公开(公告)日：2008-01-29

申请号：US11120385

申请日：2005-05-02

申请人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet ,  Wei-Wei Zhuang

IPC分类号： H01L21/00 ,  H01L21/8242

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1683

摘要： A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the hard mask, the sacrificial material, the bottom electrode; depositing a layer of silicon oxide; masking, patterning and etching to remove, in a second direction perpendicular to the first direction, a portion of the hard mask, the sacrificial material, the bottom electrode;, and over etching to an N+ layer and at least 100 nm of the silicon substrate; depositing of a layer of silicon oxide; etching to remove any remaining hard mask and any remaining sacrificial material; depositing a layer of CMR material; depositing a top electrode; applying photoresist, patterning the photoresist and etching the top electrode; and incorporating the memory array into an integrated circuit.

摘要翻译： 制造电阻器存储器阵列的方法包括制备硅衬底; 在衬底P +层上沉积底部电极，牺牲层和硬掩模层; 掩模，图案化和蚀刻以在第一方向上去除硬掩模，牺牲材料，底部电极的一部分; 沉积一层氧化硅; 掩模，图案化和蚀刻以在垂直于第一方向的第二方向上去除硬掩模，牺牲材料，底部电极的一部分，并且对N +层和至少100nm的硅衬底进行过蚀刻 ; 沉积一层氧化硅; 蚀刻以除去任何剩余的硬掩模和任何剩余的牺牲材料; 沉积一层CMR材料; 沉积顶部电极; 施加光致抗蚀剂，图案化光致抗蚀剂并蚀刻顶部电极; 并将存储器阵列并入集成电路中。

公开(公告)号：US07193267B2

公开(公告)日：2007-03-20

申请号：US10971204

申请日：2004-10-21

申请人： Sheng Teng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

IPC分类号： H01L29/76

CPC分类号： G11C11/15 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/72 ,  H01L27/24

摘要： Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions. The resistive cross-point memory device is formed by doping lines within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.

摘要翻译： 提供了电阻式交叉点存储器件，以及制造和使用方法。 存储器件由介于上电极和下电极之间的电阻存储器材料的有源层组成。 在上电极和下电极的交叉点处位于电阻性存储器材料内的位区域具有响应于施加一个或更多个电压脉冲而能够在一定范围内变化的电阻率。 可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。 在电阻性存储器材料和下电极之间的界面处形成二极管，其可以形成为掺杂区域。 电阻性交叉点存储器件通过在衬底内掺杂一个极性而形成，然后将相反极性的线的掺杂区域形成二极管。 然后在二极管上形成一层电阻记忆材料覆盖底部电极的底部电极。 然后可以以倾斜的角度添加顶部电极以形成由线和顶部电极限定的交叉点阵列。

公开(公告)号：US07009231B2

公开(公告)日：2006-03-07

申请号：US11046620

申请日：2005-01-28

申请人： Fengyan Zhang ,  Wei-Wei Zhuang ,  Jong-Jan Lee ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Wei-Wei Zhuang ,  Jong-Jan Lee ,  Sheng Teng Hsu

IPC分类号： H01L29/94

CPC分类号： H01L21/31691 ,  H01L28/55 ,  H01L41/317

摘要： A method for forming a doped PGO ferroelectric thin film, and related doped PGO thin film structures are described. The method comprising: forming either an electrically conductive or electrically insulating substrate; forming a doped PGO film overlying the substrate; annealing; crystallizing; and, forming a single-phase c-axis doped PGO thin film overlying the substrate, having a Curie temperature of greater than 200 degrees C. Forming a doped PGO film overlying the substrate includes depositing a doped precursor in the range between 0.1N and 0.5N, with a molecular formula of Pby-xMxGe3O11, where: M is a doping element; y=4.5 to 6; and, x=0.1 to 1. The element M can be Sn, Ba, Sr, Cd, Ca, Pr, Ho, La, Sb, Zr, or Sm.

摘要翻译： 描述了用于形成掺杂的PGO铁电薄膜的方法以及相关的掺杂PGO薄膜结构。 该方法包括：形成导电或电绝缘的衬底; 在衬底上形成掺杂的PGO膜; 退火; 结晶 并且形成覆盖在衬底上的单相c轴掺杂的PGO薄膜，其居里温度大于200℃。形成覆盖在衬底上的掺杂PGO膜包括在0.1N和0.5之间的范围内沉积掺杂的前体 N，具有分子式为Pb x Si x N x N x O 11，其中：M是掺杂物 元件; y = 4.5〜6; x = 0.1〜1。元素M可以是Sn，Ba，Sr，Cd，Ca，Pr，Ho，La，Sb，Zr或Sm。

公开(公告)号：US06998661B2

公开(公告)日：2006-02-14

申请号：US10385009

申请日：2003-03-10

申请人： Fengyan Zhang ,  Jer-Shen Maa ,  Wei-Wei Zhuang ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Jer-Shen Maa ,  Wei-Wei Zhuang ,  Sheng Teng Hsu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/1136 ,  H01L31/119

CPC分类号： H01L28/65 ,  C23C16/40 ,  H01L21/31691 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60 ,  H01L28/75 ,  Y10T428/24917 ,  Y10T428/2495

摘要： A method of forming an electrode and a ferroelectric thin film thereon, includes preparing a substrate; depositing an electrode on the substrate, wherein the electrode is formed of a material taken from the group of materials consisting of iridium and iridium composites; and forming a single-phase, c-axis PGO ferroelectric thin film thereon, wherein the ferroelectric thin film exhibits surface smoothness and uniform thickness. An integrated circuit includes a substrate; an electrode deposited on the substrate, wherein the electrode is formed of a material taken from the group of materials consisting of iridium and iridium composites, wherein the iridium composites are taken from the group of composites consisting of IrO2, Ir—Ta—O, Ir—Ti—O, Ir—Nb—O, Ir—Al—O, Ir—Hf—O, Ir—V—O, Ir—Zr—O and Ir—O; and a single-phase, c-axis PGO ferroelectric thin film formed on the electrode, wherein the ferroelectric thin film exhibits surface smoothness and uniform thickness.

摘要翻译： 一种在其上形成电极和铁电薄膜的方法，包括制备基板; 在所述基板上沉积电极，其中所述电极由从由铱和铱复合材料组成的材料组取得的材料形成; 并在其上形成单相c轴PGO铁电薄膜，其中铁电薄膜表现出平滑度和均匀的厚度。 集成电路包括基板; 沉积在所述基底上的电极，其中所述电极由从由铱和铱复合物组成的材料组中取得的材料形成，其中所述铱复合材料取自由IrO 2 ，Ir-Ta-O，Ir-Ti-O，Ir-Nb-O，Ir-Al-O，Ir-Hf-O，Ir-VO，Ir-Zr-O和Ir-O; 以及形成在电极上的单相c轴PGO铁电薄膜，其中铁电薄膜表现出平滑度和均匀的厚度。

公开(公告)号：US06927120B2

公开(公告)日：2005-08-09

申请号：US10442749

申请日：2003-05-21

申请人： Sheng Teng Hsu ,  Tingkal Li ,  David R. Evans ,  Wei-Wei Zhuang ,  Wei Pan

发明人： Sheng Teng Hsu ,  Tingkal Li ,  David R. Evans ,  Wei-Wei Zhuang ,  Wei Pan

IPC分类号： H01L27/10 ,  G11C11/15 ,  G11C13/00 ,  H01L45/00 ,  H01L21/8242

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1625

摘要： Asymmetrically structured memory cells and a fabrication method are provided. The method comprises: forming a bottom electrode; forming an electrical pulse various resistance (EPVR) first layer having a polycrystalline structure over the bottom electrode; forming an EPVR second layer adjacent the first layer, with a nano-crystalline or amorphous structure; and, forming a top electrode overlying the first and second EPVR layers. EPVR materials include CMR, high temperature super conductor (HTSC), or perovskite metal oxide materials. In one aspect, the EPVR first layer is deposited with a metalorganic spin coat (MOD) process at a temperature in the range between 550 and 700 degrees C. The EPVR second layer is formed at a temperature less than, or equal to the deposition temperature of the first layer. After a step of removing solvents, the MOD deposited EPVR second layer is formed at a temperature less than, or equal to the 550 degrees C.

摘要翻译： 提供了非对称结构的存储单元和制造方法。 该方法包括：形成底部电极; 在底部电极上形成具有多晶结构的电脉冲各种电阻（EPVR）第一层; 用纳米结晶或无定形结构形成邻近第一层的EPVR第二层; 并且形成覆盖在第一和第二EPVR层上的顶部电极。 EPVR材料包括CMR，高温超导体（HTSC）或钙钛矿金属氧化物材料。 在一个方面，EPVR第一层在550-700℃的温度范围内用金属有机旋涂（MOD）工艺沉积.EPVR第二层是在小于或等于沉积温度 的第一层。 在除去溶剂的步骤之后，将MOD沉积的EPVR第二层在小于或等于550℃的温度下形成。

公开(公告)号：US20050136602A1

公开(公告)日：2005-06-23

申请号：US11039536

申请日：2005-01-19

申请人： Sheng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

发明人： Sheng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

IPC分类号： H01L21/76 ,  G11C13/00 ,  H01L21/3205 ,  H01L21/8246 ,  H01L23/52 ,  H01L27/10 ,  H01L27/105 ,  H01L27/24 ,  H01L43/08 ,  H01L29/02 ,  H01L21/336 ,  H01L21/4763 ,  H01L47/00

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/77 ,  H01L27/101 ,  H01L27/24

摘要： A memory array dual-trench isolation structure and a method for forming the same have been provided. The method comprises: forming a p-doped silicon (p-Si) substrate; forming an n-doped (n+) Si layer overlying the p-Si substrate; prior to forming the n+ Si bit lines, forming a p+ Si layer overlying the n+ Si layer; forming a layer of silicon nitride overlying the p+ layer; forming a top oxide layer overlying the silicon nitride layer; performing a first selective etch of the top oxide layer, the silicon nitride layer, the p+ Si layer, and a portion of the n+ Si layer, to form n+ Si bit lines and bit line trenches between the bit lines; forming an array of metal bottom electrodes overlying a plurality of n-doped silicon (n+ Si) bit lines, with intervening p-doped (p+) Si areas; forming a plurality of word line oxide isolation structures orthogonal to and overlying the n+ Si bit lines, adjacent to the bottom electrodes, and separating the p+ Si areas; forming a plurality of top electrode word lines, orthogonal to the n+ Si bit lines, with an interposing memory resistor material overlying the bottom electrodes; and, forming oxide-filled word line trenches adjacent the word lines.

摘要翻译： 已经提供了存储器阵列双沟槽隔离结构及其形成方法。 该方法包括：形成p掺杂硅（p-Si）衬底; 形成覆盖p-Si衬底的n掺杂（n +）Si层; 在形成n + Si位线之前，形成覆盖n + Si层的p + Si层; 形成覆盖p +层的氮化硅层; 形成覆盖所述氮化硅层的顶部氧化物层; 执行顶部氧化物层，氮化硅层，p + Si层和n + Si层的一部分的第一选择性蚀刻，以在位线之间形成n + Si位线和位线沟槽; 形成覆盖多个n掺杂硅（n + Si）位线的金属底部电极阵列，具有中间p掺杂（p +）Si区域; 形成与所述n + Si位线正交并覆盖与所述底部电极相邻并分离所述p + Si区域的多个字线氧化物隔离结构; 形成与n + Si位线正交的多个顶部电极字线，覆盖在底部电极上的插入式存储电阻材料; 并且在字线附近形成氧化物填充的字线沟槽。

公开(公告)号：US06849564B2

公开(公告)日：2005-02-01

申请号：US10376796

申请日：2003-02-27

申请人： Sheng Teng Hsu ,  Wei Pan ,  Wei-Wei Zhuang ,  Fengyan Zhang

发明人： Sheng Teng Hsu ,  Wei Pan ,  Wei-Wei Zhuang ,  Fengyan Zhang

IPC分类号： G11C13/00 ,  H01L27/10 ,  H01L27/24 ,  H01L21/00

CPC分类号： H01L27/24 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/72 ,  H01L27/10

摘要： A low-capacitance one-resistor/one-diode (1R1D) R-RAM array with a floating p-well is provided. The fabrication method comprises: forming an integrated circuit (IC) substrate; forming an n-doped buried layer (buried n layer) of silicon overlying the substrate; forming n-doped silicon sidewalls overlying the buried n layer; forming a p-doped well of silicon (p-well) overlying the buried n layer; and, forming a 1R1D R-RAM array overlying the p-well. Typically, the combination of the buried n layer and the n-doped sidewalls form an n-doped well (n-well) of silicon. Then, the p-well is formed inside the n-well. In other aspects, the p-well has sidewalls, and the method further comprises: forming an oxide insulator overlying the p-well sidewalls, between the n-well and the R-RAM array.

摘要翻译： 提供具有浮动p-well的低电容单电阻/单二极管（1R1D）R-RAM阵列。 该制造方法包括：形成集成电路（IC）衬底; 形成覆盖在衬底上的硅的n掺杂掩埋层（n层）; 形成覆盖掩埋n层的n掺杂硅侧壁; 形成覆盖在掩埋n层上的硅（p阱）的p掺杂阱; 并且形成覆盖p阱的1R1D R-RAM阵列。 通常，掩埋n层和n掺杂侧壁的组合形成硅的n掺杂阱（n阱）。 然后，p阱形成在n阱内。 在其他方面，p阱具有侧壁，并且该方法还包括：在n阱和R-RAM阵列之间形成覆盖p阱侧壁的氧化物绝缘体。