公开(公告)号：US06590266B1

公开(公告)日：2003-07-08

申请号：US10064906

申请日：2002-08-28

申请人： Mu-Yi Liu ,  Tso-Hung Fan ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Tso-Hung Fan ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tao-Cheng Lu

IPC分类号： H01L2994

CPC分类号： H01L27/11266 ,  H01L27/112

摘要： A 2-bit mask ROM device and a fabrication method thereof are described. The 2-bit mask ROM device includes a substrate; a gate structure, disposed on a part of the substrate; a 2-bit code region, configured in the substrate beside both sides of the gate structure; at least one spacer, disposed on both sides of the gate structure; a buried drain region, configured in the substrate beside both sides of the spacer; a doped region, configured in the substrate between the buried drain region and the 2-bit code region, wherein the dopant type of the doped region is different from that for the 2-bit code region and the dopant concentration in the doped region is higher than that in the 2-bit code region; an insulation layer, disposed above the buried drain region; and a word line disposed on the gate structures along a same row.

摘要翻译： 描述2位掩模ROM器件及其制造方法。 2位掩模ROM器件包括衬底; 栅极结构，设置在所述衬底的一部分上; 2位代码区，配置在栅极结构的两侧旁边的基板中; 设置在所述栅极结构的两侧的至少一个间隔物; 掩埋漏极区域，被构造在所述衬底旁边的所述间隔物的两侧; 掺杂区域，配置在掩埋漏极区域和2位码区域之间的衬底中，其中掺杂区域的掺杂剂类型与2位码区域的掺杂区域不同，并且掺杂区域中的掺杂剂浓度更高 比在2位代码区域; 绝缘层，设置在所述掩埋漏极区域的上方; 以及沿同一行设置在栅极结构上的字线。

公开(公告)号：US06512696B1

公开(公告)日：2003-01-28

申请号：US09986932

申请日：2001-11-13

申请人： Tso-Hung Fan ,  Tao-Cheng Lu ,  Samuel Pan ,  Ta-Hui Wang

发明人： Tso-Hung Fan ,  Tao-Cheng Lu ,  Samuel Pan ,  Ta-Hui Wang

IPC分类号： G11C1604

CPC分类号： G11C16/12 ,  G11C16/14

摘要： A method of programming and erasing a SNNNS type non-volatile memory cell is provided. The programming operation is performed by channel hot electron injection from a drain side to an intermediate silicon nitride layer. The erasing operation is performed by channel hot hole injection from a drain side to an intermediate silicon nitride layer. The SNNNS type non-volatile memory cell provides highly efficient hot carrier injection under low applied voltages, both for programming and erasing operations. Thus, the present method provides improved performance characteristics such as shorter programming/erasing times and lower applied voltages.

摘要翻译： 提供了一种编程和擦除SNNNS型非易失性存储单元的方法。 通过从漏极侧到中间氮化硅层的通道热电子注入来进行编程动作。 擦除操作通过从漏极侧到中间氮化硅层的通道热空穴注入来进行。 SNNNS型非易失性存储单元在低施加电压下提供高效率的热载流子注入，用于编程和擦除操作。 因此，本方法提供改进的性能特征，例如较短的编程/擦除时间和较低的施加电压。

公开(公告)号：US06482709B1

公开(公告)日：2002-11-19

申请号：US09900578

申请日：2001-07-06

申请人： Han-Chao Lai ,  Hung-Sui Lin ,  Tao-Cheng Lu

发明人： Han-Chao Lai ,  Hung-Sui Lin ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L21/28035 ,  H01L21/26506 ,  H01L29/4916

摘要： A manufacturing method of a MOS transistor. A gate oxide layer and a polysilicon layer are successively formed on a substrate. A nitrogen ion implantation is performed to implant nitrogen ions into the contact region of the polysilicon layer with the gate dielectric layer. An annealing is performed in order to enlarge the polysilicon grains within the polysilicon layer. The polysilicon layer is patterned to form a gate. A dopant is implanted into the substrate on the sides of the gate, thereby forming a source/drain region.

摘要翻译： 一种MOS晶体管的制造方法。 栅极氧化层和多晶硅层依次形成在基板上。 进行氮离子注入以将氮离子注入到具有栅极介电层的多晶硅层的接触区域中。 为了扩大多晶硅层内的多晶硅晶粒，进行退火。 图案化多晶硅层以形成栅极。 掺杂剂注入栅极侧面的衬底中，由此形成源/漏区。

公开(公告)号：US06482706B1

公开(公告)日：2002-11-19

申请号：US10013982

申请日：2001-12-10

申请人： Yen-hung Yeh ,  Tso-Hung Fan ,  Mu Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

发明人： Yen-hung Yeh ,  Tso-Hung Fan ,  Mu Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A method of scaling down device dimension using spacer to confine the buried drain implant, applicable for forming memory device such as substrate/oxide/nitride/oxide/silicon (SONOS) stacked device or nitride read only memory (NROM) device. A patterned conductive layer is used as a mask for forming a pocket doped region. A spacer is formed on a side-wall of the conductive layer. As the implantation region is confined by the side-wall, a buried drain region formed by drain implantation is reduced. Therefore, the effective channel length is not reduced due to the diffusion of the buried drain region. It is thus advantageous to scale down device dimension.

摘要翻译： 一种使用间隔物来缩小器件尺寸以限制掩埋漏极注入的方法，适用于形成诸如衬底/氧化物/氮化物/氧化物/硅（SONOS）堆叠器件或氮化物只读存储器（NROM）器件的存储器件。 使用图案化导电层作为形成口袋掺杂区域的掩模。 在导电层的侧壁上形成间隔物。 当注入区被侧壁限制时，通过漏极注入形成的掩埋漏极区减小。 因此，由于埋漏区的扩散，有效沟道长度不会降低。 因此有利的是缩小器件尺寸。

公开(公告)号：US06458642B1

公开(公告)日：2002-10-01

申请号：US09990159

申请日：2001-11-20

申请人： Yen-hung Yeh ,  Tso-Hung Fan ,  Mu Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

发明人： Yen-hung Yeh ,  Tso-Hung Fan ,  Mu Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

IPC分类号： H01L218238

CPC分类号： H01L27/11568 ,  H01L27/115 ,  Y10S438/954

摘要： A method of fabricating a SONOS device, in which a first silicon oxide layer, a trapping layer, and a second silicon oxide layer are formed on the substrate. Then, a mask pattern is formed over the substrate to serve as a mask in the implantation process for forming the buried bit-lines. Afterward, a portion of the mask pattern is removed to increase the gap size of the mask pattern, then a pocket ion implantation is performed to form a pocket doped region at the periphery of the buried bit-line by using the mask pattern as a mask. Subsequently, the mask pattern is removed and a thermal process is conducted using the trapping layer as a mask to form a buried bit-line oxide layer. A word-line is subsequently formed over the substrate.

摘要翻译： 一种制造SONOS器件的方法，其中在衬底上形成第一氧化硅层，俘获层和第二氧化硅层。 然后，在用于形成掩埋位线的注入工艺中，在衬底上形成掩模图案以用作掩模。 之后，去除掩模图案的一部分以增加掩模图案的间隙尺寸，然后通过使用掩模图案作为掩模，进行袋离子注入以在掩埋位线的周围形成凹坑掺杂区域 。 随后，去除掩模图案，并使用捕获层作为掩模进行热处理，以形成掩埋的位线氧化物层。 随后在衬底上形成字线。

公开(公告)号：US20130182505A1

公开(公告)日：2013-07-18

申请号：US13349130

申请日：2012-01-12

申请人： Chuyung Liu ,  Hsing-Wen Chang ,  Yaowen Chang ,  Tao-Cheng Lu

发明人： Chuyung Liu ,  Hsing-Wen Chang ,  Yaowen Chang ,  Tao-Cheng Lu

IPC分类号： G11C16/10 ,  G11C16/06 ,  G11C16/04

CPC分类号： G11C16/10

摘要： A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a program bias pulse by biasing the bit lines and string select lines in a first condition; setting a word line coupled to a target cell to a first voltage level while the bit lines and string select lines are in the first condition; thereafter, biasing the bit lines and string select lines in a second condition; and setting the word line coupled to the target cell to a second voltage level higher than the first voltage level while the bit lines and string select lines are in the second condition. Program bias pulses produced in this manner can be used in a modulated incremental stepped pulse programming sequence.

摘要翻译： 电荷存储存储器配置在NAND阵列中，并且包括经由串选择开关耦合到位线的NAND串并且包括字线。 控制器被配置为通过在第一条件下偏置位线和串选择线来产生编程偏置脉冲; 当位线和串选择线处于第一状态时，将耦合到目标单元的字线设置为第一电压电平; 此后，将位线和串选择线偏置在第二状态中; 以及当位线和串选择线处于第二状态时，将耦合到目标单元的字线设置为高于第一电压电平的第二电压电平。 以这种方式产生的编程偏置脉冲可以用于调制增量阶梯式脉冲编程序列。

公开(公告)号：US20120286322A1

公开(公告)日：2012-11-15

申请号：US13555075

申请日：2012-07-20

申请人： SHIH-YU WANG ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

发明人： SHIH-YU WANG ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

IPC分类号： H01L29/73

CPC分类号： H01L29/7436 ,  H01L27/0251 ,  H01L27/0262 ,  H01L29/0692 ,  H01L29/78 ,  H01L29/7835 ,  H01L2924/0002 ,  H03K17/08 ,  H03K19/003 ,  H01L2924/00

摘要： A semiconductor device includes a first well region of a first conductivity type, a second well region of a second conductive type within the first well region. A first region of the first conductivity type and a second region of the second conductivity type are disposed within the second well region. A third region of the first conductivity type and a fourth region of the second conductivity type are disposed within the first well region, wherein the third region and the fourth region are separated by the second well region. The semiconductor device also includes a switch device coupled to the third region.

摘要翻译： 半导体器件包括第一导电类型的第一阱区域和第一阱区域内的第二导电类型的第二阱区域。 第一导电类型的第一区域和第二导电类型的第二区域设置在第二阱区域内。 第一导电类型的第三区域和第二导电类型的第四区域设置在第一阱区域内，其中第三区域和第四区域被第二阱区域分开。 半导体器件还包括耦合到第三区域的开关器件。

公开(公告)号：US08253165B2

公开(公告)日：2012-08-28

申请号：US12410335

申请日：2009-03-24

申请人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

发明人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

IPC分类号： H01L29/74 ,  H01L23/62

CPC分类号： H01L29/7436 ,  H01L27/0251 ,  H01L27/0262 ,  H01L29/0692 ,  H01L29/78 ,  H01L29/7835 ,  H01L2924/0002 ,  H03K17/08 ,  H03K19/003 ,  H01L2924/00

摘要： A semiconductor device includes a first well region of a first conductivity, a second well region of a second conductivity type, a source region of the second conductivity type within the first well region, and a drain region of the second conductivity type at least partially within the second well region. A well contact to the first well region is coupled to the source. A third doped region of the first conductivity type and a fourth doped region of the second conductivity type are located in the second well region. A first transistor includes the third doped region, the second well region, and the first well region. The first transistor is coupled to a switch device. A second transistor includes the second well region, the first well region, and the source region. The first and the second transistors are configured to provide a current path during an ESD event.

摘要翻译： 半导体器件包括第一导电类型的第一阱区域，第二导电类型的第二阱区域，第一阱区域内的第二导电类型的源极区域和至少部分地在第二阱区域内的第二导电类型的漏极区域 第二个井区。 与第一阱区的良好接触耦合到源。 第一导电类型的第三掺杂区域和第二导电类型的第四掺杂区域位于第二阱区域中。 第一晶体管包括第三掺杂区域，第二阱区域和第一阱区域。 第一晶体管耦合到开关器件。 第二晶体管包括第二阱区，第一阱区和源极区。 第一和第二晶体管被配置为在ESD事件期间提供电流路径。

公开(公告)号：US07875938B2

公开(公告)日：2011-01-25

申请号：US12325824

申请日：2008-12-01

申请人： Mu-Yi Liu ,  Chia-Lun Hsu ,  Ichen Yang ,  Kuan-Po Chen ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Chia-Lun Hsu ,  Ichen Yang ,  Kuan-Po Chen ,  Tao-Cheng Lu

IPC分类号： H01L29/51

CPC分类号： H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  Y10S438/981

摘要： An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased while maintaining a high breakdown voltage.

摘要翻译： 提供LDMOS器件和制造方法。 LDMOS器件具有在衬底中形成有源区和漏区的衬底。 在源极和漏极区域之间的衬底的一部分上设置绝缘层，使得在绝缘层和衬底的表面之间提供平面界面。 然后在绝缘层的一部分上形成绝缘构件，并且在绝缘构件和绝缘层的一部分上形成栅极层。 通过采用这种结构，已经发现存在能够在保持高击穿电压的同时降低导通电阻的平坦电流路径。

公开(公告)号：US20100109076A1

公开(公告)日：2010-05-06

申请号：US12264879

申请日：2008-11-04

申请人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

发明人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/0262 ,  H01L27/0251 ,  H01L29/7436

摘要： A semiconductor device includes a first well region of a first conductivity, a second well region of a second conductivity type, a source region of the second conductivity type within the first well region, and a drain region of the second conductivity type at least partially within the second well region. A well contact to the first well region is coupled to the source. A first doped region of the first conductivity type and a second doped region of the second conductivity type are located in the second well region. A first transistor includes the first doped region, the second well region, and the first well region. The first transistor is coupled to a switch device. A second transistor includes the second well region, the first well region, and the source region. The first and the second transistors are configured to provide a current path during an ESD event.

摘要翻译： 半导体器件包括第一导电类型的第一阱区域，第二导电类型的第二阱区域，第一阱区域内的第二导电类型的源极区域和至少部分地在第二阱区域内的第二导电类型的漏极区域 第二个井区。 与第一阱区的良好接触耦合到源。 第一导电类型的第一掺杂区域和第二导电类型的第二掺杂区域位于第二阱区域中。 第一晶体管包括第一掺杂区域，第二阱区域和第一阱区域。 第一晶体管耦合到开关器件。 第二晶体管包括第二阱区，第一阱区和源极区。 第一和第二晶体管被配置为在ESD事件期间提供电流路径。