公开(公告)号：US07410855B2

公开(公告)日：2008-08-12

申请号：US11841841

申请日：2007-08-20

申请人： Reika Ichihara ,  Yoshinori Tsuchiya ,  Masato Koyama ,  Akira Nishiyama

发明人： Reika Ichihara ,  Yoshinori Tsuchiya ,  Masato Koyama ,  Akira Nishiyama

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823462

摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.

公开(公告)号：US20080185656A1

公开(公告)日：2008-08-07

申请号：US11907353

申请日：2007-10-11

申请人： Masato Koyama ,  Yoshinori Tsuchiya ,  Seiji Inumiya

发明人： Masato Koyama ,  Yoshinori Tsuchiya ,  Seiji Inumiya

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823857 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate; forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively; forming a first nickel silicide having a composition of Ni/Si

摘要翻译： 可以提供一种半导体器件的制造方法，该半导体器件包括具有低阈值电压Vth和Ni-FUSI / SiON或高k栅极绝缘膜结构的CMIS。 该方法包括：在衬底中形成彼此绝缘的p型半导体区域和n型半导体区域; 在p型和n型半导体区分别形成第一和第二栅极绝缘膜; 在所述第二栅极绝缘膜上形成具有Ni / Si <31/12以上的第一栅极绝缘膜的第一镍硅化物和具有Ni / Si> 31/12的组成的第二硅化镍; 以及通过使铝通过第一硅化镍扩散，在第一硅化镍和第一栅极绝缘膜之间的界面处分离铝。

公开(公告)号：US07391085B2

公开(公告)日：2008-06-24

申请号：US11299773

申请日：2005-12-13

申请人： Reika Ichihara ,  Yoshinori Tsuchiya ,  Masato Koyama ,  Akira Nishiyama

发明人： Reika Ichihara ,  Yoshinori Tsuchiya ,  Masato Koyama ,  Akira Nishiyama

IPC分类号： H01L27/092

CPC分类号： H01L21/823857 ,  H01L21/823462

摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.

摘要翻译： 半导体器件包括半导体衬底，形成在衬底上的nMISFET，nMISFET包括形成在衬底上的第一电介质和形成在第一电介质上的第一金属栅极，并由选自Ti，Zr，Hf， Ta，Sc，Y，镧系元素和锕系和选自所述一种金属元素的硼化物，硅化物和锗化合物的一种，以及形成在所述衬底上的pMISFET，所述pMISFET包括形成在所述衬底上的第二电介质和第二金属 栅电极形成在第二电介质上并由与第一金属栅电极相同的材料制成，第二电介质面向第二金属栅电极的至少一部分由绝缘材料制成，绝缘材料与至少一部分 的第一电介质面向第一金属栅电极。

公开(公告)号：US20080135944A1

公开(公告)日：2008-06-12

申请号：US11857197

申请日：2007-09-18

申请人： Reika ICHIHARA ,  Yoshinori Tsuchiya ,  Hiroki Tanaka ,  Masato Koyama

发明人： Reika ICHIHARA ,  Yoshinori Tsuchiya ,  Hiroki Tanaka ,  Masato Koyama

IPC分类号： H01L27/092

CPC分类号： H01L21/823842 ,  H01L21/823864

摘要： A semiconductor device has an n-channel MIS transistor and a p-channel MIS transistor on a substrate. The n-channel MIS transistor includes a p-type semiconductor region formed on the substrate, a lower layer gate electrode which is formed via a gate insulating film above the p-type semiconductor region and which is one monolayer or more and 3 nm or less in thickness, and an upper layer gate electrode which is formed on the lower layer gate electrode, whose average electronegativity is 0.1 or more smaller than the average electronegativity of the lower layer gate electrode. The p-channel MIS transistor includes an n-type semiconductor region formed on the substrate and a gate electrode which is formed via a gate insulating film above the n-type semiconductor region and is made of the same metal material as that of the upper layer gate electrode.

摘要翻译： 半导体器件在衬底上具有n沟道MIS晶体管和p沟道MIS晶体管。 n沟道MIS晶体管包括形成在基板上的p型半导体区域，通过p型半导体区域上方的栅极绝缘膜形成并且为单层以上且3nm以下的下层栅电极 以及形成在下层栅电极上的上层栅电极，其平均电负性比下层栅电极的平均电负性小0.1或更小。 p沟道MIS晶体管包括形成在衬底上的n型半导体区域和通过n型半导体区域上方的栅极绝缘膜形成并由与上层相同的金属材料制成的栅电极 栅电极。

公开(公告)号：US20080128822A1

公开(公告)日：2008-06-05

申请号：US11753186

申请日：2007-05-24

申请人： Masato Koyama ,  Yoshinori Tsuchiya ,  Yuuichi Kamimuta ,  Reika Ichihara ,  Katsuyuki Sekine

发明人： Masato Koyama ,  Yoshinori Tsuchiya ,  Yuuichi Kamimuta ,  Reika Ichihara ,  Katsuyuki Sekine

IPC分类号： H01L27/092

CPC分类号： H01L27/092 ,  H01L21/28097 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

摘要： A semiconductor device includes: a p-channel MIS transistor including: a first insulating layer formed on a semiconductor region between a source region and a drain region, and containing at least silicon and oxygen; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, and a first gate electrode formed on the second insulating layer. The first and second insulating layers have a first and second region respectively. The first and second regions are in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer. Each of the first and second regions include aluminum atoms with a concentration of 1×1020 cm−3 or more to 1×1022 cm−3 or less.

摘要翻译： 半导体器件包括：p沟道MIS晶体管，包括：第一绝缘层，形成在源极区域和漏极区域之间的半导体区域上，并且至少包含硅和氧; 形成在所述第一绝缘层上并且包含铪，硅，氧和氮的第二绝缘层，以及形成在所述第二绝缘层上的第一栅电极。 第一和第二绝缘层分别具有第一和第二区域。 第一和第二区域在从第一绝缘层和第二绝缘层之间的界面的膜​​厚度方向上为0.3nm的范围内。 第一和第二区域中的每一个包括浓度为1×10 20 cm -3或更多至1×10 22 cm -3的铝原子， 3 以下。

公开(公告)号：US20070145493A1

公开(公告)日：2007-06-28

申请号：US11635040

申请日：2006-12-07

申请人： Masato Koyama ,  Reika Ichihara ,  Yoshinori Tsuchiya ,  Yuuichi Kamimuta ,  Akira Nishiyama

发明人： Masato Koyama ,  Reika Ichihara ,  Yoshinori Tsuchiya ,  Yuuichi Kamimuta ,  Akira Nishiyama

IPC分类号： H01L29/76

CPC分类号： H01L21/823842

摘要： A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.

摘要翻译： 半导体器件包括衬底，形成在衬底上的n型阱上的p沟道MIS晶体管，具有形成在其上并由Ta-C合金形成的第一栅极电介质和第一栅电极，其中晶体取向比例 膜厚方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]的TaC（111）面为80％以上，n型沟道MIS晶体管形成在p- 在基板上良好地形成具有形成在其上的第二栅极电介质和第二栅电极，并且由TaC（111）在膜厚度方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]为60％以下。

公开(公告)号：US08994034B2

公开(公告)日：2015-03-31

申请号：US13404411

申请日：2012-02-24

申请人： Tatsuo Shimizu ,  Yoshinori Tsuchiya ,  Takashi Shinohe

发明人： Tatsuo Shimizu ,  Yoshinori Tsuchiya ,  Takashi Shinohe

IPC分类号： H01L29/16 ,  H01L21/04 ,  H01L29/739 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L29/08

CPC分类号： H01L29/7802 ,  H01L21/0485 ,  H01L21/049 ,  H01L21/26506 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7813

摘要： Disclosed is a semiconductor device including: a first electrode formed of a conductive material; a p-type first silicon carbide (SiC) semiconductor section and an n-type second SiC semiconductor section 230, connected to the first electrode, containing carbon (C) such that a surface density distribution has a peak at a first interface with the first electrode.

摘要翻译： 公开了一种半导体器件，包括：由导电材料形成的第一电极; 连接到第一电极的含有碳（C）的p型第一碳化硅（SiC）半导体部分和n型第二SiC半导体部分230，使得表面密度分布在第一界面处具有与第一 电极。

公开(公告)号：US08766334B2

公开(公告)日：2014-07-01

申请号：US13602704

申请日：2012-09-04

申请人： Yoshinori Tsuchiya

发明人： Yoshinori Tsuchiya

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L27/01 ,  H01L27/12 ,  H01L27/088 ,  H01L21/336 ,  H01L21/8222

CPC分类号： H01L29/78 ,  H01L21/049 ,  H01L21/28008 ,  H01L21/28273 ,  H01L21/32155 ,  H01L29/1608 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7802

摘要： A semiconductor device of an embodiment includes: a substrate formed of a single-crystal first semiconductor; a gate insulating film on the substrate; a gate electrode including a layered structure of a semiconductor layer formed of a polycrystalline second semiconductor and a metal semiconductor compound layer formed of a first metal semiconductor compound that is a reaction product of a metal and the second semiconductor; and electrodes formed of a second metal semiconductor compound that is a reaction product of the metal and the first semiconductor, and formed on the substrate with the gate electrode interposed therebetween, and an aggregation temperature of the first metal semiconductor compound on the polycrystalline second semiconductor is lower than an aggregation temperature of the second metal semiconductor compound on the single-crystal first semiconductor, and a cluster-state high carbon concentration region is included in an interface between the semiconductor layer and the metal semiconductor compound layer.

摘要翻译： 实施例的半导体器件包括：由单晶体第一半导体形成的衬底; 基板上的栅极绝缘膜; 包括由多晶第二半导体形成的半导体层的层叠结构的栅电极和由作为金属与第二半导体的反应产物的第一金属半导体化合物形成的金属半导体化合物层; 以及由金属和第一半导体的反应产物形成的第二金属半导体化合物形成的电极，并且在基板上形成有栅极电极，多晶二次半导体上的第一金属半导体化合物的聚集温度为 低于单晶体第一半导体上的第二金属半导体化合物的聚集温度，并且在半导体层和金属半导体化合物层之间的界面中包含簇状态的高碳浓度区域。

公开(公告)号：US20120049281A1

公开(公告)日：2012-03-01

申请号：US12870011

申请日：2010-08-27

申请人： Yoshinori Tsuchiya ,  Ryosuke Iijima ,  Atsushi Yagishita

发明人： Yoshinori Tsuchiya ,  Ryosuke Iijima ,  Atsushi Yagishita

IPC分类号： H01L27/12 ,  H01L21/762

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： According to one embodiment, gate electrodes of a multi-gate field effect transistors and methods of making a gate electrode of a multi-gate field effect transistor are provided. The gate electrode can contain a semiconductor substrate; a dielectric layer over the semiconductor substrate; a fin over the dielectric layer; a gate insulating layer over the side surfaces of the fin; a gate electrode layer over the fin; and a polysilicon layer over the fin. The gate electrode does not contain a gate insulating layer over the upper surface of the dielectric layer except portions of the upper surface of the dielectric layer that contact with the side surfaces of the gate insulating layer formed over the side surface of the fin. In another embodiment, the gate electrode can contain an oxygen diffusion barrier layer or a first oxygen diffusion layer over the upper surface of the dielectric layer.

摘要翻译： 根据一个实施例，提供了多栅极场效应晶体管的栅极和制造多栅极场效应晶体管的栅电极的方法。 栅电极可以包含半导体衬底; 半导体衬底上的电介质层; 电介质层上的翅片; 在翅片的侧表面上的栅极绝缘层; 翅片上的栅极电极层; 和鳍上的多晶硅层。 栅电极除电介质层上表面的与栅极侧表面上形成的栅极绝缘层的侧面接触的部分以外，在电介质层的上表面上不包含栅极绝缘层。 在另一个实施例中，栅电极可以在电介质层的上表面上包含氧扩散阻挡层或第一氧扩散层。

公开(公告)号：US20080230804A1

公开(公告)日：2008-09-25

申请号：US12036703

申请日：2008-02-25

申请人： Yoshifumi Nishi ,  Takashi Yamauchi ,  Yoshinori Tsuchiya ,  Junji Koga

发明人： Yoshifumi Nishi ,  Takashi Yamauchi ,  Yoshinori Tsuchiya ,  Junji Koga

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/872 ,  H01L21/283

CPC分类号： H01L29/47 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/475

摘要： A semiconductor device having an electrode with reduced electrical contact resistance even where either electrons or holes are majority carriers is disclosed. This device has an n-type diffusion layer and a p-type diffusion layer in a top surface of a semiconductor substrate. The device also has first and second metal wires patterned to overlie the n-type and p-type diffusion layers, respectively, with a dielectric layer interposed therebetween, a first contact electrode for electrical connection between the n-type diffusion layer and the first metal wire, and a second contact electrode for connection between the p-type diffusion layer and the second metal wire. The first contact electrode's portion in contact with the n-type diffusion layer and the second contact electrode's portion contacted with the p-type diffusion layer are each formed of a first conductor that contains a metal and a second conductor containing a rare earth metal.

摘要翻译： 公开了一种半导体器件，其具有即使电子或空穴为多数载流子的具有降低的电接触电阻的电极。 该器件在半导体衬底的顶表面中具有n型扩散层和p型扩散层。 该装置还具有图案化的第一和第二金属线分别覆盖在n型和p型扩散层之间，介于其间的介电层，用于在n型扩散层和第一金属之间电连接的第一接触电极 电线和用于在p型扩散层和第二金属线之间连接的第二接触电极。 与n型扩散层接触的第一接触电极部分和与p型扩散层接触的第二接触电极部分分别由包含金属的第一导体和含有稀土金属的第二导体形成。