公开(公告)号：US20240345617A1

公开(公告)日：2024-10-17

申请号：US18603883

申请日：2024-03-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ranjith Kumar SAJJA ,  Sreekanth GODEY ,  Anirudh R. ACHARYA

IPC: G06F1/08 ,  G06F1/12 ,  G06F9/50 ,  G06F11/34

CPC classification number: G06F1/08 ,  G06F1/12 ,  G06F9/505 ,  G06F11/3409

Abstract: Systems and methods related to controlling clock signals for clocking shader engines modules (SEs) and non-shader-engine modules (nSEs) of a graphics processing unit (GPU) are provided. One or more dividers receive a clock signal CLK and output a clock signal CLKA to the SEs and output a clock signal CLKB to the nSEs. The frequencies of CLKA and CLKB are independently selected based on sets of performance counter data monitored at the SEs and nSEs, respectively. The clock signal frequency for either the SEs or the nSEs is reduced when the corresponding sets of performance counter data indicates a comparatively lower processing workload for the SEs or for the nSEs.

公开(公告)号：US12118357B2

公开(公告)日：2024-10-15

申请号：US17855621

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Rajesh Kumar Arunachalam ,  Manivannan Bhoopathy ,  Hon-Hin Wong ,  Scott Thomas Bingham

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/3838

Abstract: The disclosed system may include a processor configured to encode, using an encoding scheme that reduces a number of bits needed to represent one or more instructions from a set of instructions in an instruction buffer represented by a dependency matrix, a dependency indicating that a child instruction represented in the dependency matrix depends on a parent instruction represented in the dependency matrix. The processor may also be configured to store the encoded dependency in the dependency matrix and dispatch instructions in the instruction buffer based at least on decoding one or more dependencies stored in the dependency matrix for the instructions. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US12117945B2

公开(公告)日：2024-10-15

申请号：US17849117

申请日：2022-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Hideki Kanayama ,  YuBin Yao

IPC: G06F13/16

CPC classification number: G06F13/1689 ,  G06F13/1621 ,  G06F13/1642

Abstract: A data processor accesses a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent for generating a memory access request, a memory controller for providing a memory command to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, and a data fabric for converting the memory access request into the normalized request selectively for the first pseudo channel and the second pseudo channel.

公开(公告)号：US12117935B2

公开(公告)日：2024-10-15

申请号：US17852300

申请日：2022-06-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Chintan S. Patel ,  Vydhyanathan Kalyanasundharam ,  Benjamin Tsien ,  Alexander J. Branover

IPC: G06F12/00 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60 ,  G06F13/00 ,  H10B10/00 ,  H10B12/00

Abstract: A technique for operating a cache is disclosed. The technique includes utilizing a first portion of a cache in a directly accessed manner; and utilizing a second portion of the cache as a cache.

公开(公告)号：US20240333519A1

公开(公告)日：2024-10-03

申请号：US18194394

申请日：2023-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： SeyedMohammad SeyedzadehDelcheh ,  Sergey Blagodurov ,  Donald Matthews, Jr. ,  Srilatha Manne

IPC: H04L9/32

CPC classification number: H04L9/3242

Abstract: The disclosed computing device can include super flow control unit (flit) generation circuitry configured to generate a super flit containing two or more flits having two or more requests embedded therein, wherein the two or more requests have the same destination node identifiers and the super flit has a variable size based on a flit size and a number of existing requests in a source node that target a same destination node. The device can additionally include authentication circuitry configured to append a message authentication code to a last flit of the super flit. The device can also include communication circuitry configured to send the super flit to a network switch configured to route the super flit to a destination node corresponding to the same destination node identifiers. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240333307A1

公开(公告)日：2024-10-03

申请号：US18128943

申请日：2023-03-30

Applicant: XILINX, INC. ,  Advanced Micro Devices, Inc.

Inventor： Kumar RAHUL ,  John J. WUU ,  Santosh YACHARENI

IPC: H03M13/11 ,  H03M13/00

CPC classification number: H03M13/1174 ,  H03M13/616

Abstract: An integrated circuit (IC) device includes an error correction code (ECC) encoder circuitry configured to receive input data, determine min-terms in a Hamming matrix (H-Matrix) corresponding to the input data, and generate ECC data based on the min-terms and an output codeword based on the ECC data, and an error correction circuitry configured to generate a corrected output codeword based on the output codeword.

公开(公告)号：US20240331266A1

公开(公告)日：2024-10-03

申请号：US18191800

申请日：2023-03-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Trevor James Hedstrom

IPC: G06T15/06

CPC classification number: G06T15/06

Abstract: Devices and methods for rendering curves using ray tracing are provided which include tessellating a curve, representing at least a portion of an object in a scene, into a chain of capsules each comprising two spheres and a connecting cone, generating an acceleration structure comprising the chain of capsules, casting a ray in a space comprising the curve, and performing, for a capsule of the chain of capsules, a closed-form intersection test to render the curve. In a first example, the closed-form intersection test is performed using a single quadratic equation quadratic based on coefficients from input values of the two spheres. In a second example, the closed-form intersection test is performed based on an intersection between the ray and a blended sphere generated from a smallest distance between the ray and a centerline of the capsule and an offset.

公开(公告)号：US20240330134A1

公开(公告)日：2024-10-03

申请号：US18190664

申请日：2023-03-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Jerry Anton Ahrens ,  William Robert Alverson ,  Joshua Taylor Knight ,  Amitabh Mehra ,  Anil Harwani ,  Grant Evan Ley

IPC: G06F11/22 ,  G06F9/4401

CPC classification number: G06F11/2284 ,  G06F9/4401

Abstract: A system that includes at least a system memory, a chipset link, and a chipset attached memory is powered down. A boot-up process is loaded in the chipset attached memory. The boot-up process is performed for the system, via the chipset link, by the chipset attached memory. The boot-up process includes loading one or more memory testing applications. The system memory is tested using the one or more memory testing applications loaded by the chipset attached memory.

公开(公告)号：US20240329847A1

公开(公告)日：2024-10-03

申请号：US18129436

申请日：2023-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Vignesh Adhinarayanan ,  Michael Ignatowski ,  Hyung-Dong Lee

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.

公开(公告)号：US20240329720A1

公开(公告)日：2024-10-03

申请号：US18128744

申请日：2023-03-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Gia Tung Phan ,  Ashish Jain ,  Anthony Asaro ,  Dennis Kin-Wah Au

IPC: G06F1/3234 ,  G09G5/00

CPC classification number: G06F1/3265 ,  G09G5/001 ,  G09G5/363 ,  G09G2300/0842 ,  G09G2330/021 ,  G09G2360/123 ,  G09G2360/18

Abstract: An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated memories that use separate power domains. Data of a given type is stored in an interleaved manner among the multiple memories. When control circuitry detects an idle state, commands are sent to the multiple memories specifying storing data of the given type in a contiguous manner in the memories connected to multiple functional blocks. Subsequently, the control circuitry transitions all but one of the memories to the sleep state. The memories rotate amongst themselves with a single memory being in the active state and servicing requests based on which data of the given type is targeted by the requests.