公开(公告)号：US10607893B2

公开(公告)日：2020-03-31

申请号：US15898569

申请日：2018-02-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/66 ,  H01L27/088

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions; contacts connecting to the source and drain regions; contacts connecting to the gate structures which are offset from the contacts connecting to the source and drain regions; and interconnect structures in electrical contact with the contacts of the gate structures and the contacts of the source and drain regions.

公开(公告)号：US10600876B2

公开(公告)日：2020-03-24

申请号：US15974037

申请日：2018-05-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guowei Xu ,  Hui Zang ,  Rongtao Lu

IPC: H01L29/40 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3213

Abstract: A method includes forming a first cavity having a first width and a second cavity having a second width greater than the first width in a dielectric material, forming a first conformal layer in the first and second cavities, forming spacers in the first and second cavities, the spacers covering a first portion of the first conformal layer positioned on sidewalls of the first and second cavities and exposing a second portion of the first conformal layer positioned on the sidewalls of the first and second cavities, forming a material layer in the first and second cavities to cover bottom portions of the first conformal layer, performing a first etch process to remove the second portion of the first conformal layer positioned on the sidewalls of the first and second cavities, removing the spacers and the material layer, and forming a fill material in the first and second cavities.

公开(公告)号：US10593674B1

公开(公告)日：2020-03-17

申请号：US16129221

申请日：2018-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ming-Cheng Chang ,  Nigel Chan ,  Elliot John Smith

IPC: H01L29/78 ,  H01L27/092 ,  H03K19/0948 ,  H01L21/762 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/088 ,  H01L27/02

Abstract: Structures for field-effect transistors and methods for fabricating a structure for field-effect transistors. A logic cell includes first and second field-effect transistors and a well defining a back gate that is arranged beneath the first and second field-effect transistors. A dielectric layer is arranged between the well and the logic cell. A plurality of deep trench isolation regions extend through the dielectric layer and are arranged to surround the first and second field-effect transistors and the well. The back gate is shared by the first and second field-effect transistors.

公开(公告)号：US10593555B2

公开(公告)日：2020-03-17

申请号：US15925928

申请日：2018-03-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qun Gao ,  Naved Siddiqui ,  Ankur Arya ,  John R Sporre

IPC: H01L21/311 ,  H01L29/66 ,  H01L21/768 ,  H01L21/033 ,  H01L21/762 ,  H01L21/3105

Abstract: The manufacture of a FinFET device includes the formation of a composite sacrificial gate. The composite sacrificial gate includes a sacrificial gate layer such as a layer of amorphous silicon, and an etch selective layer such as a layer of silicon germanium. The etch selective layer, which underlies the sacrificial gate layer, enables the formation of a gate cut opening having a controlled critical dimension that extends through the composite sacrificial gate.

公开(公告)号：US10586762B2

公开(公告)日：2020-03-10

申请号：US15860171

申请日：2018-01-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Lars W. Liebmann

IPC: H01L23/522 ,  H01L21/28 ,  H01L23/538

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interrupted small block shape structures (e.g., cut metal lines forming cell boundaries) and methods of manufacture. The structure includes: a plurality of wiring lines with cuts that form a cell boundary; and at least one wiring line extending beyond the cell boundary and which is continuous from cell to cell.

公开(公告)号：US10580779B2

公开(公告)日：2020-03-03

申请号：US15903203

申请日：2018-02-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong Lim ,  Ryan Ryoung-Han Kim

IPC: H01L27/11 ,  G11C8/14 ,  H01L23/522 ,  H01L21/768 ,  H01L27/105 ,  H01L21/48 ,  H01L23/50

Abstract: A memory cell includes vertical transistors including first and second pass gate (PG) transistors, first and second pull-up (PU1 and PU2) transistors, and first and second pull-down (PD1 and PD2) transistors. A first bottom electrode connects bottom source/drain (SD) regions of PU1 and PU2. A second bottom electrode connects bottom SD regions of PD1 and PD2. A first shared contact connects the top SD region of PU2 to the gate structure of PU1. A second shared contact connects the top SD region of PD1 to the gate structure of PD2. A first top electrode is connected to the top SD regions of PG1, PU1 and the second shared contact to define a first storage node of the memory cell. A second top electrode is connected to the top SD regions of PG2, PU2 and the first shared contact to define a second storage node of the memory cell.

公开(公告)号：US10580696B1

公开(公告)日：2020-03-03

申请号：US16106246

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sean Xuan Lin ,  Christian Witt ,  Mark V. Raymond ,  Nicholas V. LiCausi ,  Errol Todd Ryan

IPC: H01L23/12 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/532 ,  H01L21/288

Abstract: Structures for interconnects and methods of forming interconnects. An interconnect opening in a dielectric layer includes a first portion and a second portion arranged over the first portion. A first conductor layer composed of a first metal is arranged inside the first portion of the interconnect opening. A second conductor layer composed of a second metal is arranged inside the second portion of the interconnect opening. The first metal is ruthenium.

公开(公告)号：US10580581B2

公开(公告)日：2020-03-03

申请号：US15815308

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert J. Fox, III ,  Lili Cheng ,  Roderick A. Augur

IPC: H01G4/30 ,  H01G4/252 ,  H01G4/005 ,  H01G4/12 ,  H01L49/02 ,  H01G4/012 ,  H01G4/33 ,  H01G4/232

Abstract: Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. The MIM capacitor includes a layer stack with a first electrode, a second electrode, and a third electrode. The layer stack includes a pilot opening extending at least partially through at least one of the first electrode, the second electrode, and the third electrode. A dielectric layer is arranged over the metal-insulator-metal capacitor, and includes a via opening extending vertically to the pilot opening. A via is arranged in the via opening and the pilot opening. The pilot opening has a cross-sectional area that is less than a cross-sectional area of the via opening.

公开(公告)号：US20200066883A1

公开(公告)日：2020-02-27

申请号：US16108152

申请日：2018-08-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Hui Zang ,  Bingwu Liu ,  Manoj Joshi ,  Jae Gon Lee ,  Hsien-Ching Lo ,  Zhaoying Hu

IPC: H01L29/66 ,  H01L21/308 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234

Abstract: Methods form devices by patterning a lower layer to form a fin, and forming a sacrificial gate along sidewalls of the fin. Such methods form a mask with cut openings on the sacrificial gate and remove sections of the fin and the sacrificial gate exposed through the cut openings to divide the fin into fin portions and create cut areas between the fin portions. Additionally, these methods remove the mask, epitaxially grow source/drains in the cut areas, replace the sacrificial gate with a gate conductor, and form a gate contact on the gate conductor over a center of the fin portions.

公开(公告)号：US10573593B2

公开(公告)日：2020-02-25

申请号：US15983168

申请日：2018-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sean Xuan Lin ,  Xunyuan Zhang ,  Shao Beng Law ,  James Jay McMahon

IPC: H01L21/4763 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to metal interconnect structures for super (skip) via integration and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer including an interconnect and wiring structure; and at least one upper wiring layer with one or more via interconnect and wiring structures located above the second wiring layer. The one or more via interconnect and wiring structures partially including a first metal material and remaining portions with a conductive material over the first metal material. A skip via passes through the second wiring layer and extends to the one or more wiring structures of the first wiring layer. The skip via partially includes the metal material and remaining portions of the skip via includes the conductive material over the first metal material.