公开(公告)号：US06987695B2

公开(公告)日：2006-01-17

申请号：US10397882

申请日：2003-03-25

Applicant: Jongmin Park ,  Li-Chun Li

Inventor： Jongmin Park ,  Li-Chun Li

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/10 ,  G11C16/30

Abstract: In some embodiments, of the present invention, data are written to a plurality of nonvolatile memory cells (Q0, Q15) as follows. A data writing signal is supplied to one of the memory cells (Q0) but not to both of the memory cells. Then data writing signals are supplied to both of the memory cells simultaneously.

Abstract translation: 在一些实施例中，如下所述，将数据写入多个非易失性存储单元（Q 0，Q 15）。 数据写入信号被提供给存储单元（Q 0）中的一个而不是两个存储单元。 然后，数据写入信号同时被提供给两个存储单元。

公开(公告)号：US20050263488A1

公开(公告)日：2005-12-01

申请号：US10943936

申请日：2004-09-20

Applicant: Hong Change ,  Hung Lu

Inventor： Hong Change ,  Hung Lu

IPC: B44C1/22 ,  H01L21/00 ,  H01L21/302 ,  H01L21/306 ,  H01L21/311

CPC classification number: H01L21/67086 ,  H01L21/31111

Abstract: The present etching system includes a processing tank with an etching solution containing silicon, a cooling tank, a pre-heating tank, a first pipe for transferring the etching solution from the processing tank to the cooling tank, a second pipe for transferring the etching solution from the cooling tank to the pre-heating tank, and a third pipe for transferring the etching solution from the pre-heating tank to the processing tank. The present method for treating the etching solution first performs an etching process using the etching solution, which is then cooled to a first temperature to form a silicon-saturated etching solution. After silicon-containing particles larger than a predetermined size are filtered out, the silicon-saturated etching solution is heated to a second temperature to form a non-saturated etching solution for performing another etching process later. The second temperature is preferably at least 10° C. higher than the first temperature.

Abstract translation: 本蚀刻系统包括具有含硅蚀刻液的处理槽，冷却槽，预热槽，将蚀刻液从处理槽输送到冷却槽的第一管，用于将蚀刻液 从冷却槽到预热槽，以及用于将蚀刻液从预热槽输送到处理槽的第三管。 本蚀刻溶液的处理方法首先使用蚀刻液进行蚀刻处理，然后冷却至第一温度，形成硅饱和蚀刻液。 在大于预定尺寸的含硅颗粒被滤出之后，将硅饱和蚀刻溶液加热到第二温度以形成用于稍后进行另一蚀刻处理的非饱和蚀刻溶液。 第二温度优选比第一温度高至少10℃。

公开(公告)号：US06960808B2

公开(公告)日：2005-11-01

申请号：US10707358

申请日：2003-12-08

Applicant: Yu-Piao Wang

Inventor： Yu-Piao Wang

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/76 ,  H01L27/108 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L21/76897 ,  H01L21/28044 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/823475 ,  H01L23/5222 ,  H01L29/6653 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor device is described. A gate dielectric layer is formed on a substrate, and several gate structures having a gate conductor, a cap layer and spacers are formed on the gate dielectric layer. A mask layer is formed over the substrate covering a portion of the gate structures. Removing the cap layer and spacers that are not covered by the mask layer. After the mask layer is removed, a dielectric layer is formed over the substrate covering the gate structures. A self-aligned contact-hole is formed in the dielectric layer. A conductive layer is formed in the self-aligned contact hole and on the dielectric layer. Since the cap layer and spacers that are not covered by the mask layer are removed and substituted by the dielectric layer having lowerdielectric constant property, the parasitic capacitance can be reduced.

Abstract translation: 对半导体装置的制造方法进行说明。 在基板上形成栅极介电层，在栅极电介质层上形成具有栅极导体，盖层和间隔物的多个栅极结构。 在覆盖栅极结构的一部分的衬底上形成掩模层。 去除未被掩模层覆盖的盖层和间隔物。 在去除掩模层之后，在覆盖栅极结构的衬底的上方形成介电层。 在电介质层中形成自对准的接触孔。 在自对准接触孔和电介质层上形成导电层。 由于未被掩模层覆盖的覆盖层和间隔物被具有较低介电常数特性的介电层所取代并代替，所以可以减小寄生电容。

公开(公告)号：US06955964B2

公开(公告)日：2005-10-18

申请号：US10702711

申请日：2003-11-05

Applicant: Barbara A. Haselden ,  John Lee

Inventor： Barbara A. Haselden ,  John Lee

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/8247

CPC classification number: H01L21/32139 ,  H01L21/28123 ,  H01L21/28273 ,  H01L21/32137

Abstract: A method of forming a double gate structure including sidewalls of substantially similar vertical profile. One photoresist masking step is used to define the top gate, which is then used as a mask to define the bottom gate. The bottom polysilicon layer is etched by a physical and chemical process combination to form a bottom gate with vertical sidewalls substantially inline with the sidewalls of the top gate.

公开(公告)号：US20050212032A1

公开(公告)日：2005-09-29

申请号：US11143991

申请日：2005-06-02

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/8247 ,  H01L29/76

CPC classification number: H01L29/42344 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11531

Abstract: In a nonvolatile memory, the select gates (144S) are formed from one conductive layer (e.g. polysilicon or polyside), and the wordlines (144) interconnecting the select gates are made from a different conductive layer (e.g. metal). The wordlines overlie an dielectric (302, 304, 310) formed over control gate lines (134). Each control gate line provides control gates for one column of the memory cells. The adjacent control gate lines for the adjacent memory columns are spaced from each other. The dielectric thickness can be controlled to reduce the capacitance between the wordlines and the control gates. In some embodiments, the floating gates (120) are fabricated in a self-aligned manner using an isotropic etch of the floating gate layer.

Abstract translation: 在非易失性存储器中，选择栅极（144S）由一个导电层（例如多晶硅或多边形）形成，并且互连选择栅极的字线（144）由不同的导电层（例如金属）制成。 字线覆盖在控制栅线（134）上形成的电介质（302,304,310）。 每个控制栅极线提供一列存储器单元的控制栅极。 用于相邻存储器列的相邻控制栅极线彼此间隔开。 可以控制电介质厚度以减小字线和控制门之间的电容。 在一些实施例中，使用浮动栅极层的各向同性蚀刻，以自对准的方式制造浮置栅极（120）。

公开(公告)号：US06936521B2

公开(公告)日：2005-08-30

申请号：US10750805

申请日：2004-01-02

Applicant: Tony Chien

Inventor： Tony Chien

IPC: G03F9/00 ,  H01L23/544 ,  H01L21/76

CPC classification number: G03F9/7084 ,  G03F9/7076 ,  G03F9/708

Abstract: An alignment mark is made of at least two nonparallel trenches having two reducing-width-to-zero ends. The displacement bias error, produced by a process bias error, of the centerlines of the trenches is zero where the width of the two trenches is zero. Hence, the alignment target on a substrate can be reproduced.

Abstract translation: 对准标记由至少两个具有两个减小宽度到零端的不平行沟槽制成。 由沟槽中心线产生的位移偏移误差为零，两个沟槽的宽度为零。 因此，可以再现衬底上的取向靶。

公开(公告)号：US20050154484A1

公开(公告)日：2005-07-14

申请号：US10949361

申请日：2004-09-27

Applicant: Yung-Yao Lee ,  Tseng-Yung Wang

Inventor： Yung-Yao Lee ,  Tseng-Yung Wang

IPC: G03F7/20 ,  G06F19/00

CPC classification number: G03F7/705 ,  G03F7/70533 ,  G03F7/70633

Abstract: A photolithographic parameter feedback system is described. The photolithographic parameter feedback system includes a database containing substrate history information of a lot having at least one measurement data after exposure of a pre-layer of substrates of a predetermined lot and an exposure tool history information having at least one measurement data after exposure of a predetermined layer of substrates of a pre-lot, and an exposure tool exposing the substrates of the predetermined lot, wherein at least one exposure parameter thereof is updated by feedback of the substrate history information of the lot and the exposure tool history information.

Abstract translation: 描述光刻参数反馈系统。 光刻参数反馈系统包括数据库，该数据库包含具有在预定批次的基板的预先曝光之后具有至少一个测量数据的批次的基板历史信息和在曝光之后具有至少一个测量数据的曝光工具历史信息 预定批次的预定层的基板和暴露预定批次的基板的曝光工具，其中通过对批次的基板历史信息和曝光工具历史信息的反馈来更新其至少一个曝光参数。

公开(公告)号：US06903022B2

公开(公告)日：2005-06-07

申请号：US10262939

申请日：2002-10-03

Applicant: Hsin-Tang Peng ,  Yung-Ching Wang ,  Teng-Chun Yang

Inventor： Hsin-Tang Peng ,  Yung-Ching Wang ,  Teng-Chun Yang

IPC: H01L21/60 ,  H01L21/8239 ,  H01L21/302

CPC classification number: H01L21/76897 ,  H01L27/1052

Abstract: A method of forming contact holes. A dielectric liner is comformally formed on a substrate, parts of the dielectric liner between the second and the third conducting structure are removed, a conductive liner is conformally formed on the substrate, and parts of the metal layer are removed to leave parts thereof between the second and the third conducting structure. An ILD layer is then formed on the entire surface of the substrate, and a patterned photoresist layer is formed on the ILD layer. Finally, the ILD layer is etched using the patterned photoresist layer as a mask to form a first contact hole, a second contact hole, and a third contact hole in the ILD layer at the same time.

Abstract translation: 一种形成接触孔的方法。 电介质衬垫被合成地形成在衬底上，去除第二和第三导电结构之间的电介质衬垫的部分，导电衬垫保形地形成在衬底上，并且去除金属层的一部分以将其部分留在 第二和第三导电结构。 然后在衬底的整个表面上形成ILD层，并且在ILD层上形成图案化的光致抗蚀剂层。 最后，使用图案化的光致抗蚀剂层作为掩模来蚀刻ILD层，以在ILD层中同时形成第一接触孔，第二接触孔和第三接触孔。

公开(公告)号：US06872621B1

公开(公告)日：2005-03-29

申请号：US10758624

申请日：2004-01-14

Applicant: Yung-Hsien Wu

Inventor： Yung-Hsien Wu

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8242 ,  H01L21/331

CPC classification number: H01L28/84 ,  H01L21/31111 ,  H01L21/32134 ,  H01L27/1087

Abstract: A method for removal of hemispherical grained silicon (HSG) in a deep trench is described. A buried silicon germanium (SiGe) layer serving as an etch stop layer is formed in the collar region of the trench, followed by depositing a HSG layer. The HSG layer is then successfully striped by wet etching with a potassium hydroxide/propanone/water etchant, that is, without damage to the trench sidewalls, since a good etch rate selectivity between the HSG layer and the SiGe layer is obtained by the wet etchant. In addition, no etch stop layer exists between the HSG layer and the bottom of the trench when manufacturing trench capacitors in accordance with the method; capacitance degradation is therefore not of concern.

Abstract translation: 描述了在深沟槽中去除半球状晶粒硅（HSG）的方法。 在沟槽的轴环区域中形成用作蚀刻停止层的掩埋硅锗（SiGe）层，随后沉积HSG层。 然后通过用氢氧化钾/丙酮/水蚀刻剂进行湿蚀刻成功地条纹HSG层，即不损坏沟槽侧壁，因为通过湿蚀刻剂获得HSG层和SiGe层之间的良好蚀刻速率选择性 。 此外，根据该方法制造沟槽电容器时，在HSG层和沟槽的底部之间不存在蚀刻停止层; 因此，电容劣化不是关心的。

公开(公告)号：US06868050B1

公开(公告)日：2005-03-15

申请号：US09639376

申请日：2000-08-15

Applicant: Paul Phuc Tran ,  Wei Qian

Inventor： Paul Phuc Tran ,  Wei Qian

IPC: G11B7/007 ,  G11B7/125 ,  G11B7/00 ,  G11B5/09

CPC classification number: G11B7/1267 ,  G11B7/00736

Abstract: The present invention provides a method and system for calibration of writing to an optical medium. The method includes: sampling marks in a calibration area of the optical medium; and converting the sampled marks into a digital format utilizing an ADC, the ADC also utilized by a servo control. The present invention provides a controller with an integrated servo and recording processor which allows a single ADC to be used for converting sample marks used in calibrating the writing to an optical media. No separate subsystem for converting sample marks is thus necessary. Less components are required, reducing the cost of manufacturing the controller. With less components, the risk of component failure is reduced as well.

Abstract translation: 本发明提供了一种用于校准写入光学介质的方法和系统。 该方法包括：在光学介质的校准区域中采样标记; 并使用ADC将采样标记转换为数字格式，ADC也由伺服控制使用。 本发明提供一种具有集成伺服和记录处理器的控制器，其允许单个ADC用于将用于校准写入的采样标记转换为光学介质。 因此，不需要用于转换样品标记的独立子系统。 需要较少的部件，降低制造控制器的成本。 使用较少的组件，组件故障的风险也会降低。