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公开(公告)号：US09330779B2
公开(公告)日：2016-05-03
申请号：US14594473
申请日：2015-01-12
发明人： Man L Mui , Yingda Dong , Chris Avila
CPC分类号： G11C16/3459 , G11C11/5635 , G11C11/5642 , G11C13/004 , G11C16/26 , G11C16/344 , G11C16/3454
摘要： A number (Nwl) of programmed word lines in a block of NAND strings is determined by measuring a reference combined current (Iref) in the block when all of the memory cells are in a conductive state. Subsequently, to determine if a word line is a programmed word line, an additional combined current (Iadd) in the block is measured with a demarcation voltage applied to the selected word line. The selected word line is determined to be programmed word lines if Idd is less than Iref by at least a margin. Nwl can be used to adjust an erase-verify test of an erase operation by making the erase-verify test relatively hard to pass when the number is relatively small and relatively easy to pass when the number is relatively large. Or, Nwl can be used to identify a next word line to program in the block.
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82.发明授权Data storage device and method to correct bit values using multiple read voltages 有权数据存储装置和使用多个读取电压校正位值的方法公开(公告)号：US09329934B2
公开(公告)日：2016-05-03
申请号：US14698626
申请日：2015-04-28
CPC分类号： G06F11/1068 , G06F11/1048 , G11C29/52
摘要： A data storage device includes a memory including a group of storage elements. The memory is configured to read the group of the storage elements. A controller is coupled to the memory. The controller is configured to, in response to a first error correction code (ECC) procedure determining that a first plurality of bit values obtained using a first read voltage to read the group of storage elements is uncorrectable, instruct the memory to read the group of the storage elements using a second read voltage to obtain a second plurality of bit values. The controller is further configured to compare the first plurality of bit values with the second plurality of bit values to identify a first set of bits having different values in the first plurality of bit values as compared to the second plurality of bit values and to change one or more values of the first plurality of bit values for one or more bits in the first set of bits to generate a first plurality of corrected bit values.
摘要翻译： 数据存储装置包括包括一组存储元件的存储器。 内存被配置为读取存储元件的组。 控制器耦合到存储器。 控制器被配置为响应于第一纠错码（ECC）过程，确定使用第一读取电压获得的第一多个比特值来读取该组存储元件是不可校正的，指示存储器读取该组 所述存储元件使用第二读取电压来获得第二多个位值。 控制器还被配置为将第一多个比特值与第二多个比特值进行比较，以识别与第二多个比特值相比在第一多个比特值中具有不同值的第一组比特，并且改变一个 或多于第一组位中的一个或多个比特的第一多个比特值的值，以生成第一多个校正比特值。
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公开(公告)号：US20160118136A1
公开(公告)日：2016-04-28
申请号：US14525813
申请日：2014-10-28
发明人： Huai-Yuan Tseng , Deepanshu Dutta
CPC分类号： G11C16/3495 , G11C11/5628 , G11C11/5635 , G11C13/0004 , G11C13/0035 , G11C13/0064 , G11C13/0069 , G11C16/0483 , G11C16/3422 , G11C16/349 , G11C29/52 , G11C2211/5621 , G11C2211/5644
摘要： Methods for detecting and correcting defects in a memory array during a memory operation are described. The memory operation may comprise a programming operation or an erase operation. In some cases, a Control Gate Short to Substrate (CGSS) defect, in which a control gate of a NAND memory has been shorted to the substrate, may have a defect signature in which a word line shows a deviation in the number of programming loop counts associated with programming data into memory cells connected to the word line. The deviation in the number of programming loop counts may be detected by comparing a baseline programming loop count (e.g., derived from programming a set of one or more word lines prior to programming the word line with the CGSS defect) with a programming loop count associated with programming the word line with the CGSS defect.
摘要翻译： 描述了在存储器操作期间检测和校正存储器阵列中的缺陷的方法。 存储器操作可以包括编程操作或擦除操作。 在某些情况下，NAND存储器的控制栅极已经短路到衬底的控制栅极到基板（CGSS）缺陷可能具有缺陷签名，其中字线表示编程环路数量的偏差 与将数据编程连接到与字线连接的存储器单元中的计数。 可以通过比较基准编程循环计数（例如，从在编程字线与CGSS缺陷编程之前编程一组或多个字线的集合）与相关联的编程循环计数相比较来检测编程循环计数数量的偏差 用CGSS缺陷对字线进行编程。
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公开(公告)号：US20160118131A1
公开(公告)日：2016-04-28
申请号：US14522901
申请日：2014-10-24
发明人： Yingda Dong , Jiahui Yuan , Jian Chen
CPC分类号： G11C16/3427 , G11C7/04 , G11C16/10 , G11C16/3431 , G11C16/3459
摘要： Techniques are provided for reducing program disturb in a memory device. The techniques include compensating for a temperature in the memory device to reduce the upshift in the threshold voltage (Vth) of erased-state memory cells. A minimum allowable program pulse duration increases with temperature to account for an increase in the attenuation of a program pulse along a word line. A program pulse duration which accounts for reduced channel boosting at relatively high temperatures is reduced as the temperature increases. An optimum program pulse duration is based on the larger of these durations. The optimum program pulse duration can also be based on factors such as a measure of program disturb or a memory hole width. Program disturb can also be reduced by easing the requirements of a verify test for the highest data state.
摘要翻译： 提供了用于减少存储器件中的程序干扰的技术。 这些技术包括补偿存储器件中的温度以减少擦除状态存储器单元的阈值电压（Vth）的升档。 最小可允许编程脉冲持续时间随着温度而增加，以增加沿着字线的编程脉冲的衰减。 在相对较高的温度下减少通道增压的程序脉冲持续时间随着温度的升高而降低。 最佳编程脉冲持续时间是基于这些持续时间中较大的一个。 最佳编程脉冲持续时间也可以基于诸如程序干扰的测量或存储器孔宽度的因素。 程序干扰也可以通过缓解对最高数据状态的验证测试的要求来降低。
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85.发明授权公开(公告)号：US09325276B2
公开(公告)日：2016-04-26
申请号：US14596789
申请日：2015-01-14
IPC分类号： G11C5/14 , H03B5/04 , H03B5/24 , H03K3/03 , G11C16/32 , G11C16/10 , G11C16/30 , G11C16/12 , H03K3/011 , H03K3/0231 , G11C16/04
CPC分类号： H03B5/04 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/30 , G11C16/32 , H03B5/24 , H03K3/011 , H03K3/02315 , H03K3/0315
摘要： Apparatus and methods are provided for a temperature-compensated oscillator adapted to receive an input reference current. The apparatus and methods include or provide a temperature coefficient control circuit adapted to adjust the input reference current based on temperature information, wherein the temperature coefficient control circuit receives a first signal corresponding to the temperature information at a first signal node, and a second signal corresponding to a trimmed bias signal at a second signal node.
摘要翻译： 提供适用于接收输入参考电流的温度补偿振荡器的装置和方法。 该装置和方法包括或提供一种温度系数控制电路，其适于基于温度信息调整输入参考电流，其中温度系数控制电路接收与第一信号节点处的温度信息对应的第一信号，以及相应的第二信号 到第二信号节点处的修整偏置信号。
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86.发明授权Fast adaptive trimming of operating parameters for non-volatile memory devices 有权快速自适应调整非易失性存储器件的工作参数公开(公告)号：US09324441B1
公开(公告)日：2016-04-26
申请号：US14600693
申请日：2015-01-20
发明人： Grishma Shah
CPC分类号： G11C16/16 , G11C7/10 , G11C16/26 , G11C16/344 , G11C16/3459 , G11C16/349 , G11C29/028
摘要： As memory devices scale down, the controller may use different sets of trim values for read/program/erase operations for different blocks based on the amount of wear a block has experienced. To facilitate this process, when the controller issues series of commands, a set of parameters for the operations are initially transferred into latches that are normally used for user data, after which they are transferred into the registers used to hold the parameters while the operation is performed. This allows for read, write and erase parameters to be updated with minimal time penalty and on the fly, allowing for these trim values to be changed more frequently and without the need to add extra registers on the memory circuit.
摘要翻译： 随着存储器件缩小，控制器可以基于块经历的磨损量，针对不同块的读/写/擦除操作使用不同的修整值集合。 为了方便这个过程，当控制器发出一系列命令时，一组用于操作的参数最初被传送到通常用于用户数据的锁存器中，之后它们被传送到用于保存参数的寄存器，而操作是 执行。 这允许以最小的时间损失更新读取，写入和擦除参数，并且可以更快速地更改这些修剪值，而无需在存储器电路上添加额外的寄存器。
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公开(公告)号：US09323662B2
公开(公告)日：2016-04-26
申请号：US13793581
申请日：2013-03-11
申请人： Lee M. Gavens
发明人： Lee M. Gavens
CPC分类号： G06F12/0246 , G06F12/0238 , G06F12/0607 , G06F12/10 , G06F2212/7201 , G06F2212/7208
摘要： A system and method for using virtual physical addresses in a non-volatile memory device are disclosed. The physical layout of the non-volatile memory device may have physical die that are not a power-of-2 in number. In order to advantageously use the power-of-2 die number, which enables using a power-of-2 die interleave, a virtual physical addressing scheme is used. In particular, the virtual physical addressing scheme includes virtual die and virtual blocks, wherein the virtual die are a power-of-2 in number. Further, a conversion between the virtual physical addressing scheme and the actual physical addressing scheme is provided. In this way, for certain operations of the memory device, the virtual addressing scheme is used. For other operations, such as reading from, writing to or erasing, the actual physical addressing scheme is used.
摘要翻译： 公开了一种在非易失性存储器件中使用虚拟物理地址的系统和方法。 非易失性存储器件的物理布局可以具有不是2的幂数的物理管芯。 为了有利地使用能够使用2功率管芯交错的2功率的芯片数量，使用虚拟物理寻址方案。 具体地，虚拟物理寻址方案包括虚拟虚拟块和虚拟块，其中虚拟管芯的数量是2的幂数。 此外，提供虚拟物理寻址方案和实际物理寻址方案之间的转换。 以这种方式，对于存储器件的某些操作，使用虚拟寻址方案。 对于其他操作，例如读取，写入或擦除，使用实际的物理寻址方案。
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88.发明授权Memory system and method for improving read latency of a high-priority partition 有权用于提高高优先级分区的读延迟的内存系统和方法公开(公告)号：US09323657B1
公开(公告)日：2016-04-26
申请号：US14594934
申请日：2015-01-12
发明人： Rotem Sela , Eliad Adi Klein , Miki Sapir
IPC分类号： G06F12/02
CPC分类号： G06F11/073 , G06F11/0793 , G06F2212/1024
摘要： A memory system and method for improving read latency of a high-priority partition are provided. In one embodiment, a memory system receives a command to store data in the memory. The memory system determines if the command specified that the data is to be stored in a standard partition in the memory or in a high-priority partition in the memory. If the command specified that the data is to be stored in a standard partition in the memory, the memory system stores the data using a first write technique. If the command specified that the data is to be stored in a high-priority partition in the memory, the memory system stores the data using a second write technique, wherein the second write technique provides improved read latency of the stored data. Other embodiments are disclosed.
摘要翻译： 提供了一种用于提高高优先级分区的读延迟的存储器系统和方法。 在一个实施例中，存储器系统接收将数据存储在存储器中的命令。 存储器系统确定命令是否将数据存储在存储器中的标准分区中或存储器中的高优先级分区中。 如果命令指定将数据存储在存储器中的标准分区中，则存储器系统使用第一写入技术存储数据。 如果命令指定数据要存储在存储器中的高优先级分区中，则存储器系统使用第二写入技术来存储数据，其中第二写入技术提供所存储数据的改进的读延迟。 公开了其他实施例。
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89.发明申请Weak Erase After Programming To Improve Data Retention In Charge-Trapping Memory 有权编程后弱化擦除电荷捕获存储器中的数据保留公开(公告)号：US20160111164A1
公开(公告)日：2016-04-21
申请号：US14518340
申请日：2014-10-20
发明人： Hong-Yan Chen , Yingda Dong , Ching-Huang Lu
CPC分类号： G11C16/14 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/3404 , G11C16/3409 , G11C16/3413
摘要： Techniques are provided to improve long term data retention in a charge-trapping memory device. In addition to a primary charge-trapping layer in which most charges are stored, the memory device may include a tunneling layer comprising an engineered tunneling barrier such as oxide-nitride-oxide. The nitride in the tunneling layer may also store some charges after programming. After the programming, a data retention operation is performed which de-traps some electrons from the tunneling layer, in addition to injecting holes into the tunneling layer which form neutral electron-hole dipoles in place of electrons. These mechanisms tend to lower threshold voltage. Additionally, the data retention operation redistributes the electrons and the holes inside the charge-trapping layer, resulting in an increase in threshold voltage which roughly cancels out the decrease when the data retention operation is optimized.
摘要翻译： 提供技术来改善电荷俘获存储器件中的长期数据保持。 除了存储大多数电荷的主电荷捕获层之外，存储器件可以包括隧道层，其包括工程化隧道势垒，例如氧化物 - 氮化物 - 氧化物。 在编程之后，隧道层中的氮化物也可能存储一些电荷。 在编程之后，除了将空穴注入到形成中性电子 - 空穴偶极子的隧道层中以代替电子之外，还执行了从隧道层去除一些电子的数据保留操作。 这些机制倾向于降低阈值电压。 此外，数据保持操作将电荷和空穴重新分布在电荷俘获层内部，导致阈值电压的增加，这在数据保持操作优化时大致抵消了减少。
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公开(公告)号：US09318210B1
公开(公告)日：2016-04-19
申请号：US14611997
申请日：2015-02-02
发明人： James V. Hart , Kenneth Louie , Khanh Nguyen , Man Mui
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/3459 , G11C2211/5621
摘要： When applying a sensing voltage at one end of a word line of a non-volatile memory circuit, an initial kick, where the voltage is initially raised somewhat above its final desired voltage, is used. Using on-chip circuitry for the determination of the RC time constant of the word lines allows for this kick to be trimmed to the specifics of the circuit. To further improve settling times for read operations is NAND type architectures, when raising the voltage to the desired read level on a selected word line, a reverse kick, where the non-selected word line's voltage is dropped briefly, can be applied to neighboring non-selected word lines.
摘要翻译： 当在非易失性存储器电路的字线的一端应用感测电压时，使用其中电压最初升高到其最终期望电压以上的初始踢脚。 使用片上电路来确定字线的RC时间常数允许将该脚趾修剪到电路的细节。 为了进一步提高读操作的建立时间，NAND型架构在将选定字线上的电压提高到期望的读取电平时，可以将未选择的字线的电压短暂地下降的反向跳转应用于相邻的非线性 - 选择的字线。
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