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139 条记录 (耗时 0.028 秒)

    Method for making planarized polycide
    81.
    发明授权
    Method for making planarized polycide 失效
    平面化多晶硅化合物的制备方法

    公开(公告)号：US06194296B1

    公开(公告)日：2001-02-27

    申请号：US08558564

    申请日：1995-10-31

    申请人： Chuen-Der Lien

    发明人： Chuen-Der Lien

    IPC分类号： H01L213205

    CPC分类号： H01L21/32115 ,  H01L21/28044 ,  H01L21/28123 ,  H01L21/28273 ,  H01L29/4925

    摘要： Planarized polycide structures and methods for making the same. One embodiment includes a semiconductor structure having an irregular upper surface caused, for example, by the presence of field oxide surrounding an active region of an FET. A layer of polysilicon is located over the irregular upper surface of the semiconductor structure. The polysilicon layer has a substantially flat upper surface. A metal silicide layer is located over the flat upper surface of the polysilicon layer to form a polycide structure. This planarized polycide structure can be used, for example, as a gate electrode in an FET. In another embodiment, the planarized polycide structure includes a first polysilicon layer located over a semiconductor substrate. The polysilicon layer has an irregular upper surface. A dielectric layer is located over a portion of the upper surface of the polysilicon layer, such that the upper surface of the dielectric layer and the portion of the upper surface of the polysilicon layer which does not underlie the dielectric layer are substantially co-planar. A metal silicide layer is located over the co-planar upper surfaces of the polysilicon layer and the dielectric layer. The present invention also includes methods for fabricating planarized polycide structures.

    摘要翻译： 平面化的聚酰胺结构及其制造方法。 一个实施例包括具有不规则上表面的半导体结构，其例如由围绕FET的有源区域的场氧化物的存在引起。 多晶硅层位于半导体结构的不规则上表面上方。 多晶硅层具有基本平坦的上表面。 金属硅化物层位于多晶硅层的平坦上表面上方以形成多晶硅结构。 该平坦化的多晶硅化物结构可以用作例如FET中的栅电极。 在另一个实施方案中，平坦化的多晶硅化物结构包括位于半导体衬底上的第一多晶硅层。 多晶硅层具有不规则的上表面。 电介质层位于多晶硅层的上表面的一部分上方，使得电介质层的上表面和不在电介质层下面的多晶硅层的上表面的部分基本上是共面的。 金属硅化物层位于多晶硅层和电介质层的共面上表面之上。 本发明还包括制造平面化多晶硅化物结构的方法。

    Identical gate conductivity type static random access memory cell
    82.
    发明授权
    Identical gate conductivity type static random access memory cell 有权
    相同的栅极导电型静态随机存取存储单元

    公开(公告)号：US06191460B1

    公开(公告)日：2001-02-20

    申请号：US09390454

    申请日：1999-09-07

    申请人： Jeong Y. Choi ,  Chuen-Der Lien

    发明人： Jeong Y. Choi ,  Chuen-Der Lien

    IPC分类号： H02L2994

    CPC分类号： H01L27/11 ,  H01L27/1104

    摘要： A static random access memory cell is given increased stability and latch-up immunity by using N-type gate NMOS transistors and P-type gate PMOS transistors in the control and sensing circuits, but using the same gate conductivity type for both the NMOS and PMOS memory cell transistors. For example, both NMOS and PMOS memory cell transistors have N-type gates. Weakening the memory cell load transistors by lightly doping the source and/or drain regions further enhances stability.

    摘要翻译： 通过在控制和感测电路中使用N型栅极NMOS晶体管和P型栅极PMOS晶体管，给静态随机存取存储器单元提供了更高的稳定性和闭锁抑制能力，但对NMOS和PMOS使用相同的栅极导电类型 存储单元晶体管。 例如，NMOS和PMOS存储单元晶体管都具有N型栅极。 通过轻掺杂源极和/或漏极区来减弱存储器单元负载晶体管进一步增强了稳定性。

    Method of forming air gaps for reducing interconnect capacitance
    83.
    发明授权
    Method of forming air gaps for reducing interconnect capacitance 失效
    形成气隙以减少互连电容的方法

    公开(公告)号：US6136687A

    公开(公告)日：2000-10-24

    申请号：US978967

    申请日：1997-11-26

    申请人： Shih-Ked Lee ,  Chu-Tsao Yen ,  Cheng-Chen Calvin Hsueh ,  James R. Shih ,  Chuen-Der Lien

    发明人： Shih-Ked Lee ,  Chu-Tsao Yen ,  Cheng-Chen Calvin Hsueh ,  James R. Shih ,  Chuen-Der Lien

    IPC分类号： H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/7682

    摘要： A method for manufacturing integrated circuits increases the aspect ratio of the electrical conductor members connected to the circuits by increasing the effective height of the conductors, either by forming a thicker layer of conductor material prior to patterning the conductor members, or by adding a capping dielectric layer to the conductor material prior to patterning, or by overetching the dielectric material underlying the conductor members.The structure is then covered by a dielectric layer having poor step coverage, resulting in a number of voids and open spaces in the dielectric layer to thereby reduce the dielectric constant between the patterned conductors. A plasma etchback of the dielectric layer is employed to open and shape additional voids and open spaces in the dielectric layer. This is followed by the deposition of a second layer of dielectric material to seal the structure, including any open spaces in the first layer of dielectric material.

    摘要翻译： 制造集成电路的方法通过增加导体的有效高度来增加与电路连接的电导体部件的纵横比，通过在构图导体部件之前形成较厚的导体材料层，或者通过添加封盖电介质 在图案化之前或通过过蚀刻导体部件下面的电介质材料的层。 然后，该结构被具有差的阶梯覆盖的介电层覆盖，导致介电层中的空隙和开放空间的数量，从而降低图案化导体之间的介电常数。 采用电介质层的等离子体回蚀来打开和形成电介质层中的附加空隙和开放空间。 之后沉积第二层电介质材料以密封结构，包括第一层电介质材料中的任何开放空间。

    High voltage tolerable input buffer and method for operating same
    84.
    发明授权
    High voltage tolerable input buffer and method for operating same 失效
    高电压容忍输入缓冲器及其操作方法

    公开(公告)号：US6104229A

    公开(公告)日：2000-08-15

    申请号：US649898

    申请日：1996-05-02

    申请人： Chuen-Der Lien

    发明人： Chuen-Der Lien

    IPC分类号： H03K19/003 ,  H03K19/0185 ,  H03K19/094

    CPC分类号： H03K19/00315

    摘要： An input buffer for use in an integrated circuit having a V.sub.CC voltage supply and a V.sub.SS voltage supply. The input buffer includes a p-channel field effect transistor (FET) having a source region coupled to the V.sub.CC voltage supply, a drain region coupled to a bias circuit, and a gate electrode coupled to an input terminal. The bias circuit maintains a voltage at the drain region of the p-channel FET which is slightly greater than the V.sub.SS supply voltage when a logic high voltage is applied to the input terminal. In an alternate embodiment, the input buffer includes an n-channel FET having a drain region coupled to the V.sub.CC voltage supply, a source region coupled to the output terminal and a gate electrode coupled to the input terminal. The bias circuit maintains a voltage at the source of the n-channel FET which is greater than the V.sub.SS supply voltage when a logic low voltage is applied to the input terminal.

    摘要翻译： 一种用于具有VCC电压源和VSS电压源的集成电路中的输入缓冲器。 输入缓冲器包括具有耦合到VCC电压源的源极区域，耦合到偏置电路的漏极区域和耦合到输入端子的栅极电极的p沟道场效应晶体管（FET）。 当逻辑高电压施加到输入端子时，偏置电路在p沟道FET的漏极区域保持稍大于VSS电源电压的电压。 在替代实施例中，输入缓冲器包括具有耦合到VCC电压源的漏极区域的n沟道FET，耦合到输出端子的源极区域和耦合到输入端子的栅极电极。 当向输入端子施加逻辑低电压时，偏置电路在n沟道FET的源极处保持大于VSS电源电压的电压。

    Electrically programmable interlevel fusible link for integrated circuits
    86.
    发明授权
    Electrically programmable interlevel fusible link for integrated circuits 失效
    用于集成电路的电可编程的层间可熔链路

    公开(公告)号：US5949127A

    公开(公告)日：1999-09-07

    申请号：US870333

    申请日：1997-06-06

    申请人： Chuen-Der Lien ,  Anita M. Hansen ,  David J. Pilling

    发明人： Chuen-Der Lien ,  Anita M. Hansen ,  David J. Pilling

    IPC分类号： H01L23/525 ,  H01L29/94

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011

    摘要： In a multi-level interconnect structure, a fusible material fills an opening in an isolation layer disposed between two interconnect levels or between an interconnect level and a device layer. The opening which may be, for example, a contact hole or a via, may be fabricated using processes generally used to fabricate normally sized vias and contact holes. The opening has a cross-sectional area A reduced by a factor of x relative to normally sized openings. Because the fusible interlevel interconnection has a reduced cross-sectional area, a programming current develops a destructive programming current density within fusible interlevel interconnection while current densities in coupled conductors, including normally sized vias and contacts, remain within long term reliability limits. Read/write circuitry connected to the fusible interlevel interconnection supports the programming current and supports a read current. The read current is regulated such that a responsive current density in a nonprogrammed fusible interlevel interconnection does not exceed long term reliability limits.

    摘要翻译： 在多层互连结构中，可熔材料填充设置在两个互连层之间或互连层与器件层之间的隔离层中的开口。 可以使用通常用于制造通常尺寸的通孔和接触孔的工艺来制造可以是例如接触孔或通孔的开口。 开口具有相对于正常尺寸的开口减小X因子的横截面面积A. 由于易熔层间互连具有减小的横截面积，因此编程电流在易熔层间互连中产生破坏性编程电流密度，而耦合导体（包括通常尺寸的通孔和触点）中的电流密度仍然保持在长期可靠性限度内。 连接到易熔层互连的读/写电路支持编程电流并支持读取电流。 读取电流被调节，使得非编程的可熔层间互连中的响应电流密度不超过长期可靠性限制。

    Non-reactive anti-reflection coating
    87.
    发明授权
    Non-reactive anti-reflection coating 失效
    非反应性防反射涂层

    公开(公告)号：US5834125A

    公开(公告)日：1998-11-10

    申请号：US78929

    申请日：1993-06-16

    申请人： Chuen-Der Lien

    发明人： Chuen-Der Lien

    IPC分类号： G03F7/09 ,  H01L21/027 ,  H01L21/3213 ,  B32B17/00

    CPC分类号： G03F7/091 ,  H01L21/0276 ,  H01L21/3213 ,  G03F7/09 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/31667

    摘要： An anti-reflection coating is provided that has a barrier layer and an anti-reflective layer. The barrier layer stops reactions between the anti-reflective layer and underlying layers or substrates, does not make the anti-reflective layer reflective, and preferably does not react with either the reflective layer or the anti-reflective layer. In particular embodiments, the barrier layer is a thin layer of silicon dioxide SiO.sub.2 or silicon nitride Si.sub.3 N.sub.4, and the anti-reflective layer is titanium-tungsten TiW, titanium nitride TiN, or amorphous silicon.

    摘要翻译： 提供了具有阻挡层和抗反射层的抗反射涂层。 阻挡层停止抗反射层与下层或基底之间的反应，不使防反射层反射，并且优选不与反射层或抗反射层反应。 在具体实施方案中，阻挡层是二氧化硅SiO 2或氮化硅Si 3 N 4的薄层，抗反射层是钛 - 钨TiW，氮化钛TiN或非晶硅。

    Method for fabricating a CMOS device
    88.
    发明授权
    Method for fabricating a CMOS device 失效
    CMOS器件制造方法

    公开(公告)号：US5750424A

    公开(公告)日：1998-05-12

    申请号：US764662

    申请日：1996-12-10

    申请人： Jeong Yeol Choi ,  Chung-Jen Chien ,  Chung-Chyung Han ,  Chuen-Der Lien

    发明人： Jeong Yeol Choi ,  Chung-Jen Chien ,  Chung-Chyung Han ,  Chuen-Der Lien

    IPC分类号： H01L21/762 ,  H01L21/8238

    CPC分类号： H01L21/823864 ,  H01L21/76202 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823892

    摘要： A process for fabricating a CMOS structure using a single masking step to define lightly-doped source and drain regions for both N- and P-channel devices. The process forms disposable spacers adjacent to gate structures and at least one retrograde well. Retrograde wells are formed using one or more charged ions at different energy levels. In addition, heavily-doped source and drain regions are formed using blanket implants of two different conductivities into a semiconductor substrate having two contiguous wells of opposite conductivity type. By blanket implanting a first dopant into both wells, and then selectively implanting a second dopant, the diffusion of the second dopant is partially suppressed by the first dopant. The partial suppression of first dopant results in shallow implants being formed. Also disclosed is a process for forming contact openings and contact implants.

    摘要翻译： 一种使用单个掩模步骤制造CMOS结构以定义用于N沟道和P沟道器件的轻掺杂源极和漏极区的工艺。 该过程形成邻近门结构和至少一个逆行井的一次性间隔物。 使用不同能级的一种或多种带电离子形成逆行阱。 此外，使用具有两个不同导电性的覆盖植入物形成具有相反导电类型的两个连续的阱的半导体衬底，形成重掺杂源极和漏极区域。 通过将第一掺杂剂一次性地注入两个孔中，然后选择性地注入第二掺杂剂，第二掺杂剂的扩散部分被第一掺杂剂抑制。 第一掺杂物的部分抑制导致形成浅的植入物。 还公开了一种用于形成接触开口和接触植入物的方法。

    Changed device model electrostatic discharge protection circuit for output drivers and method of implementing same
    89.
    发明授权
    Changed device model electrostatic discharge protection circuit for output drivers and method of implementing same 失效
    改变输出驱动器的器件型静电放电保护电路及其实现方法

    公开(公告)号：US5729419A

    公开(公告)日：1998-03-17

    申请号：US560608

    申请日：1995-11-20

    申请人： Chuen-Der Lien

    发明人： Chuen-Der Lien

    IPC分类号： H03K17/082 ,  H02H9/00

    CPC分类号： H03K17/0822

    摘要： An output circuit for an integrated circuit which provides protection for the integrated circuit during a charged device model (CDM) electrostatic discharge (ESD) event. The output circuit includes a first FET connected across a first voltage supply rail (V.sub.CC or ground) and an output pad. A first driving circuit drives the gate of the first transistor. One or more CDM ESD protection circuits are connected between the gate of the first transistor and the output pad. These protection circuits provide relatively low impedance current paths which minimize current flow through the gate oxide layer of the first FET during a CDM ESD event.

    摘要翻译： 一种用于集成电路的输出电路，其在充电装置模型（CDM）静电放电（ESD））事件期间为集成电路提供保护。 输出电路包括跨第一电压供电轨（VCC或地）连接的第一FET和输出垫。 第一驱动电路驱动第一晶体管的栅极。 一个或多个CDM ESD保护电路连接在第一晶体管的栅极和输出焊盘之间。 这些保护电路提供相对低阻抗的电流路径，其在CDM ESD事件期间最小化通过第一FET的栅极氧化物层的电流。