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103 条记录 (耗时 0.019 秒)

    Integrated semiconductor memory
    81.
    发明授权
    Integrated semiconductor memory 失效
    集成半导体存储器

    公开(公告)号：US4742489A

    公开(公告)日：1988-05-03

    申请号：US811886

    申请日：1985-12-20

    申请人： Kurt Hoffmann

    发明人： Kurt Hoffmann

    IPC分类号： G06F11/22 ,  G11C29/00 ,  G11C29/26 ,  G11C29/34 ,  G11C7/00

    CPC分类号： G11C29/26

    摘要： An integrated semiconductor memory includes n identical memory cell fields each having a data width equal to m, n.multidot.m data lines for writing-in and reading-out memory data into and out of the memory cell fields, m first data separators for applying the memory data as a function of addressing data when written-in, m second data separators for selecting one of the n data lines in response to the addressing data. It further has evaluation circuits connected to n of the n.multidot.m data lines parallel to the respective second data separators. It also has third data separators connected between each of the m data input terminals and the n of n.multidot.m data lines parallel to the first data separators for transferring the memory data in parallel to all of the n data lines in response to the control signal, and fourth data separators each preceding a respective one of the m data output terminals for selectively feeding the memory data selected by the second data separators or the output signal generated by the evaluation circuit to the data output terminals in response to the control signal and a complementary signal.

    摘要翻译： 集成半导体存储器包括n个相同的存储单元场，每个存储单元场均具有数据宽度等于m，n×m个数据线，用于将存储器数据写入和读出存储单元区域; m个第一数据分离器，用于施加存储器数据 作为在写入时寻址数据的功能，m个第二数据分离器用于响应于寻址数据选择n条数据线之一。 它还具有连接到平行于各个第二数据分离器的n×m数据线中的n个的评估电路。 它还具有连接在每个m个数据输入端之间的第三数据分离器和与第一数据分离器并联的n×m个数据线的n个，用于响应于控制信号并行传送存储数据到所有n条数据线;以及 第四数据分离器，每个在m个数据输出端子中的相应一个之前，用于响应于控制信号和互补信号选择性地将由第二数据分离器选择的存储器数据或由评估电路产生的输出信号馈送到数据输出端子 。

    Monolithically integrated semiconductor circuit with transistors
    82.
    发明授权
    Monolithically integrated semiconductor circuit with transistors 失效
    具有晶体管的单片集成半导体电路

    公开(公告)号：US4549096A

    公开(公告)日：1985-10-22

    申请号：US533615

    申请日：1983-09-19

    申请人： Kurt Hoffmann

    发明人： Kurt Hoffmann

    IPC分类号： H01L27/04 ,  G05F3/20 ,  H01L21/822 ,  H01L27/02 ,  H01L29/78 ,  H03K19/0185 ,  H03F3/42

    CPC分类号： G05F3/205 ,  H01L27/0222

    摘要： Monolithically integrated semiconductor circuit with transistors, the semiconductor circuit proper having elements thereof formed on the front side of a semiconductor chip, the latter also having at the surface thereof two supply terminals actable upon by a respective supply potential and connected, on the one hand, to the elements of the semiconductor circuit proper and, on the other hand, to an additional circuit part for generating a substrate bias applied to a substrate region occupying the rear side of the semiconductor chip and, respectively, to at least one semiconductor zone belonging to the semiconductor circuit proper and to a gate electrode on the front side of the semiconductor chip which controls the semiconductor zone and is insulated therefrom, including a series connection of the substrate bias generator and the semiconductor circuit proper dividing a voltage present at the two supply terminals of the semiconductor chip in a manner that a reference potential required for the semiconductor circuit proper is produced.

    摘要翻译： 具有晶体管的半导体集成半导体电路，其半导体电路本体具有形成在半导体芯片的前侧上的元件，半导体芯片的表面还具有可由相应电源供应的两个电源端子，一方面， 另一方面涉及用于产生施加到占据半导体芯片背面的衬底区域的衬底偏置的附加电路部分，并且分别连接到属于该半导体电路的至少一个半导体区域的附加电路部分 半导体电路本体和半导体芯片的前侧上的栅极电极，其控制半导体区域并与其绝缘，包括基板偏置发生器和正确划分两个电源端子处的电压的半导体电路的串联连接 以使得所需的参考电位成为半导体芯片的方式 r生产半导体电路。

    Monolithically integrated semiconductor memory
    83.
    发明授权
    Monolithically integrated semiconductor memory 失效
    单片集成半导体存储器

    公开(公告)号：US4441171A

    公开(公告)日：1984-04-03

    申请号：US339156

    申请日：1982-01-13

    申请人： Kurt Hoffmann

    发明人： Kurt Hoffmann

    IPC分类号： G11C11/419 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/24 ,  G11C7/00

    CPC分类号： G11C11/4091

    摘要： Monolithically integrated semiconductor memory, including a matrix of identical memory cells disposed in a set of row members and a set of column members, each of the memory cells including a single MOS-field effect transistor and a storage capacitor, a comparator, and a comparison cell, the comparison cell being in the form of a memory cell including a single MOS-field effect transistor and a storage capacitor, the comparator and the comparison cell being assigned to each of the members of one of the sets, each of the comparators within the matrix of single-transistor memory cells including a flip-flop memory cell constructed in complimentary MOS-technology.

    摘要翻译： 单片集成半导体存储器，包括设置在一组行成员中的相同存储器单元的矩阵和一组列构件，每个存储单元包括单个MOS场效应晶体管和存储电容器，比较器和比较 单元，比较单元是包括单个MOS场效应晶体管和存储电容器的存储单元的形式，比较器和比较单元被分配给每个组中的每一个，每个比较器内部 包括以补偿MOS技术构成的触发器存储单元的单晶体管存储单元的矩阵。

    One-transistor dynamic ram with poly bit lines
    84.
    发明授权
    One-transistor dynamic ram with poly bit lines 失效
    具有多位线的单晶体管动态RAM

    公开(公告)号：US4334236A

    公开(公告)日：1982-06-08

    申请号：US67926

    申请日：1979-08-20

    申请人： Kurt Hoffmann ,  Heinrich Schulte

    发明人： Kurt Hoffmann ,  Heinrich Schulte

    IPC分类号： H01L27/10 ,  G11C11/35 ,  G11C11/404 ,  H01L21/31 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108 ,  H01L29/78 ,  G11C11/40 ,  H01L29/04

    CPC分类号： G11C11/404 ,  G11C11/35 ,  H01L23/522 ,  H01L27/10805 ,  H01L2924/0002

    摘要： An MOS integrated semiconductor memory is disclosed with memory locations arranged in lines and columns. The memory locations in each case contain two one-transistor memory cells. For each memory location, two MOS transistors of the two one-transistor memory cells are controlled in common by means of a word line which runs in a line direction. The two MOS transistors are each coupled on a respective bit line which runs on one side of the memory locations in a column direction. Electrodes of the MOS memory capacitors and the gates of the MOS transistors of the one-transistor memory cells are formed by a first polysilicon layer and a second polysilicon layer, respectively. For reduction of area and also of bit line capacitance as well as at the same time raising the memory capacitance, the invention provides that the bit lines are provided as a third polysilicon layer forming polysilicon paths, and that the polysilicon paths which form the bit lines are coupled on only via limited doped connection zones in a semiconductor substrate which contains the memory cells of the MOS transistors.

    摘要翻译： 公开了一种MOS集成半导体存储器，其具有以行和列布置的存储器位置。 每种情况下的存储器位置都包含两个单晶体管存储单元。 对于每个存储器位置，两个单晶体管存储单元的两个MOS晶体管通过在线方向上运行的字线被共同控制。 两个MOS晶体管分别耦合在沿列方向在存储单元的一侧上运行的相应位线上。 MOS存储电容器的电极和单晶体管存储单元的MOS晶体管的栅极分别由第一多晶硅层和第二多晶硅层形成。 为了减小面积和位线电容以及同时提高存储电容，本发明提供了将位线设置为形成多晶硅路径的第三多晶硅层，并且形成位线的多晶硅路径 仅通过包含MOS晶体管的存储单元的半导体衬底中的有限掺杂连接区域耦合。

    Static three-transistor-storage element
    85.
    发明授权
    Static three-transistor-storage element 失效
    静态三晶体管存储元件

    公开(公告)号：US4000427A

    公开(公告)日：1976-12-28

    申请号：US679089

    申请日：1976-04-21

    申请人： Kurt Hoffmann

    发明人： Kurt Hoffmann

    IPC分类号： G11C11/41 ,  G11C11/412 ,  H03K3/3565 ,  G11C11/40 ,  H03K3/295 ,  H03K3/353

    CPC分类号： H03K3/3565 ,  G11C11/412

    摘要： A three-transistor storage element is disclosed which includes a first load element, a first field effect transistor and a second load element connected in series between first and second terminal lines of a voltage supply. Node points are located at opposite ends of the first transistor in the series path between the first load element and the first transistor and between the second load element and the first transistor. A second field effect transistor is connected between the first terminal line and the second node point. The gate of said second transistor is connected to the first node point. The gate of the first transistor is connected to a reference voltage. An address field effect transistor is connected between a bit line and the second node point and the gate of said address transistor is connected to a word line. A modified form of this storage element is one in which the load elements are in the form of fourth and fifth field effect transistors. The gates of these fourth and fifth field effect transistors are connected to the source of each of the fourth and fifth transistors, respectively. A third form of the present invention has the gates of the address transistor and the gate of the first transistor connected together and to the word line. A fourth form of the invention has the gates of the first and fifth transistors and the address transistor connected together to the word line.

    摘要翻译： 公开了一种三晶体管存储元件，其包括串联连接在电压源的第一和第二端子线之间的第一负载元件，第一场效应晶体管和第二负载元件。 节点位于第一负载元件和第一晶体管之间以及第二负载元件与第一晶体管之间的串联路径中的第一晶体管的相对端。 第二场效应晶体管连接在第一端子线和第二节点之间。 所述第二晶体管的栅极连接到第一节点。 第一晶体管的栅极连接到参考电压。 地址场效应晶体管连接在位线和第二节点之间，并且所述地址晶体管的栅极连接到字线。 该存储元件的修改形式是其中负载元件是第四和第五场效应晶体管形式的形式。 这些第四和第五场效应晶体管的栅极分别连接到第四和第五晶体管的源极。 本发明的第三种形式具有地址晶体管的栅极和第一晶体管的栅极连接在一起并连接到字线。 本发明的第四种形式具有第一和第五晶体管的栅极和与字线连接在一起的地址晶体管。

    Method for improving the read signal in a memory having passive memory elements
    89.
    发明申请
    Method for improving the read signal in a memory having passive memory elements 有权
    一种用于在具有无源存储器元件的存储器中改善读取信号的方法

    公开(公告)号：US20050128796A1

    公开(公告)日：2005-06-16

    申请号：US11004880

    申请日：2004-12-07

    申请人： Kurt Hoffmann

    发明人： Kurt Hoffmann

    IPC分类号： G11C7/10 ,  G11C11/14 ,  G11C11/00

    CPC分类号： G11C7/1069 ,  G11C7/1051 ,  G11C11/14 ,  G11C2211/5647

    摘要： A method for improving read signals in a memory including passive memory elements provided at crossover locations of word and bit lines, and in which stored digital information is represented by a respective resistance of the memory elements includes: determining logic levels of information bits to be written to the memory elements associated with a respective bit line; inverting the logic levels of the information bits if more than half of information bits to be written to the memory elements associated with the respective bit line have a logic level corresponding to a low-value resistance of the memory elements; writing the information bits to the memory elements; and generating an additional check bit, a logic level of which represents an inverted or non-inverted state of the information bits.

    摘要翻译： 一种用于改善存储器中的读取信号的方法，包括在字和位线的交叉位置处提供的无源存储器元件，并且其中存储的数字信息由存储器元件的相应电阻表示，包括：确定要写入的信息位的逻辑电平 到与相应位线相关联的存储器元件; 如果要写入到与相应位线相关联的存储器元件的信息位的一半以上具有与存储器元件的低值电阻相对应的逻辑电平，则反转信息位的逻辑电平; 将信息位写入存储元件; 并产生附加校验位，其逻辑电平表示信息位的反相或非反相状态。